High-speed flip-flop semiconductor device

• US 10,141,916 B2
• Filed: 08/24/2016
• Issued: 11/27/2018
• Est. Priority Date: 09/01/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min Su
• Primary Examiner(s): Luu, An
• Application Number:
  US15/245,239
• Publication Number:
  US 20170063349A1
• Time in Patent Office: 825 Days
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

Claims

1. A semiconductor circuit comprising:

a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;

a second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal; and

a third logic gate that receives inputs of a second input signal and a scan-enable signal and performs a third logical operation on the second input signal and the scan-enable signal to generate the first input signal.

2. The semiconductor circuit of claim 1, further comprising an inverter that receives an input of the first input signal and performs an inversion logical operation to output the inverted output signal.

3. The semiconductor circuit of claim 1, wherein:

the first logic gate comprises at least one of a 3 input NAND logic gate, an OR-NAND composite logic gate and an AND-OR-NAND composite logic gate, and

the second logic gate comprises at least one of a 3 input NAND logic gate, a 2AND-OR-NAND composite logic gate and an AND-OR-NAND composite logic gate.

4. The semiconductor circuit of claim 1, wherein:

the first logic gate comprises at least one of a 3 input NOR logic gate, an AND-NOR composite logic gate and an OR-AND-NOR composite logic gate, and

the second logic gate comprises at least one of a 3 input NOR logic gate, a 2OR-AND-NOR composite logic gate and an OR-AND-NOR composite logic gate.

5. The semiconductor circuit of claim 1, wherein the second input signal is an enable signal.

6. The semiconductor circuit of claim 1, further comprising an inverter that receives an input of the first output signal and performs an inversion logical operation to output a second output signal.

7. The semiconductor circuit of claim 1, further comprising a latch that receives inputs of the first output signal and an inverted signal of the clock signal to output a second output signal.

8. The semiconductor circuit of claim 1, wherein the third logic gate also receives a third input signal and performs the third logical operation on the second input signal, the third input signal, and the scan-enable signal to produce the first input signal.

9. The semiconductor circuit of claim 1, wherein the third logic gate comprises a composite logic gate that performs a first sub-logical operation on the second input signal and a third input signal to generate a first intermediate signal and performs a second sub-logical operation on the first intermediate signal and the scan-enable signal to generate the first input signal.

10. A semiconductor circuit comprising:

a first logic gate that directly receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal;

a second logic gate that directly receives inputs of the first input signal and the feedback signal, and performs a second logical operation; and

a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a third logical operation to output the feedback signal.

11. The semiconductor circuit of claim 10, wherein:

the first logic gate comprises at least one of a 3 input NAND logic gate and an OR-NAND composite logic gate, and

the third logic gate comprises at least one of a 3 input NAND logic gate and a 2AND-OR-NAND composite logic gate.

12. The semiconductor circuit of claim 10, wherein:

the first logic gate comprises at least one of a 3 input NOR logic gate and an AND-NOR composite logic gate, and

the third logic gate comprises at least one of the 3 input NOR logic gate and a 2OR-AND-NOR composite logic gate.

13. The semiconductor circuit of claim 10, further comprising a fourth logic gate that receives an enable signal and a scan enable signal and performs a fourth logical operation on the enable signal and the scan enable signal to generate the first input signal.

14. The semiconductor circuit of claim 10, further comprising an inverter that receives an input of the first output signal and performs an inversion logical operation to output a second output signal.

15. The semiconductor circuit of claim 10, further comprising a latch that receives inputs of the first output signal and an inverted signal of the clock signal to output a second output signal.

16. The semiconductor circuit of claim 10, further comprising a fourth logic gate that receives a second input signal and a scan enable signal and performs a fourth logical operation on the second input signal and the scan enable signal to generate the first input signal.

17. A semiconductor circuit comprising:

a first logic gate that receives inputs of a second input signal, a clock signal and a feedback signal and performs a second sub-logical operation to output a first output signal, the second input signal being generated by performing a first sub-logical operation on an inverted signal of the first output signal and a first input signal;

a second logic gate that receives inputs of the first input signal and the feedback signal to perform a first logical operation; and

a third logic gate that receives inputs of the first output signal of the first logic gate, the clock signal and an output signal of the second logic gate and performs a second logical operation to output the feedback signal.

18. The semiconductor circuit of claim 17, further comprising an inverter that receives an input of the first output signal and performs an inversion logical operation to output the inverted signal of the first output signal.

19. The semiconductor circuit of claim 17, wherein:

the first logic gate comprises an OR-NAND composite logic gate,

the second logic gate comprises at least one of a NAND logic gate and an OR-NAND composite logic gate, and

the third logic gate comprises at least one of a 3 input NAND logic gate and a 2AND-OR-NAND composite logic gate.