Three state latch

• US 10,141,930 B2
• Filed: 06/04/2013
• Issued: 11/27/2018
• Est. Priority Date: 06/04/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Gotterba, Andreas J., Wang, Jesse S.
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/909,981
• Publication Number:
  US 20140354330A1
• Time in Patent Office: 2,002 Days
• Field of Search: None
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/09425 Multistate logic H03K19/096 takes precedence
• CPC Class Codes: H03K 3/038 Multistable circuits

Abstract

Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Claims

1. An electronic circuit comprising a single latch having three stable states, said latch comprising three inputs and three outputs for indicating said three stable states, and wherein said latch is configured wherein all said three outputs reflect a change at any one of said inputs in not more than two gate delays.

2. The electronic circuit of claim 1 wherein the three inputs are for controlling said three stable states.

3. The electronic circuit of claim 1 configured wherein a zero on an input forces a corresponding output to one.

4. The electronic circuit of claim 1 configured wherein a one on less than all inputs forces a corresponding output to zero.

5. The electronic circuit of claim 1 configured wherein when all inputs are set to one, a previous state of the latch is retained and output on said outputs.

6. The electronic circuit of claim 1 wherein said single latch circuit is configured to operate without a clock signal.

7. The electronic circuit of claim 1 wherein said single latch circuit has no transitory states.

8. The electronic circuit of claim 1 wherein said single latch circuit comprises a maximum of 18 transistors.

9. An electronic circuit comprising:

a single latch having 2ⁿ−

1 stable states, said latch comprising;

n outputs for indicating said 2ⁿ−

1 stable states,

wherein n is an integer greater than 2.

10. The electronic circuit of claim 9 comprising exactly n outputs for indicating said 2ⁿ−

1 stable states.

11. The electronic circuit of claim 9 wherein said latch is configured wherein all said n outputs reflect a change at any one input in not more than two gate delays.

12. The electronic circuit of claim 9 further comprising n inputs for controlling said 2ⁿ−

1 stable states.

13. The electronic circuit of claim 12 configured so that a zero on an input forces a corresponding output to one.

14. The electronic circuit of claim 12 configured so that a one on less than all inputs forces a corresponding output to zero.

15. The electronic circuit of claim 12 configured so that when all inputs are set to one, a previous state of the latch is retained and output on said outputs.

16. An electronic circuit comprising a single latch having n stable states, said latch comprising n outputs for indicating said n stable states, and wherein said latch is configured wherein all said n outputs reflect a change at any one input in not more than two gate delays, wherein n is an integer greater than 3.

17. The electronic circuit of claim 16 comprising n inputs for controlling said n stable states.

18. The electronic circuit of claim 16 configured wherein a zero on an input forces a corresponding output to one.

19. The electronic circuit of claim 16 configured wherein a one on less than all inputs forces a corresponding output to zero.

20. The electronic circuit of claim 16 configured wherein when all inputs are set to one, a previous state of the latch is retained and output on said outputs.