Configurable computing array using two-sided integration
First Claim
Patent Images
1. A configurable computing-array die, comprising:
- a semiconductor substrate having a first side and a second side;
an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and
, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;
an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements;
whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements and said configurable logic elements, wherein said complex math function is a combination of at least said first and second math functions.
0 Assignments
0 Petitions
Accused Products
Abstract
The present invention discloses a configurable computing array using two-sided integration. It is a monolithic integrated circuit comprising at least a configurable computing element located on one side of the substrate and at least a configurable logic element on the other side of the substrate. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.
13 Citations
20 Claims
-
1. A configurable computing-array die, comprising:
-
a semiconductor substrate having a first side and a second side; an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and
, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements; whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements and said configurable logic elements, wherein said complex math function is a combination of at least said first and second math functions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A configurable computing-array die, comprising:
-
a semiconductor substrate having a first side and a second side; an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and
, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements; whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements, said configurable logic elements and said configurable interconnects, wherein said complex math function is a combination of at least said first and second math functions. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeChengDu HaiCun IP Technology LLC, Guobiao Zhang
-
Original AssigneeChengDu HaiCun IP Technology LLC, Guobiao Zhang
-
InventorsZhang, Guobiao
-
Primary Examiner(s)Richardson, Jany
-
Application NumberUS15/793,933Publication NumberTime in Patent Office398 DaysField of SearchNoneUS Class CurrentCPC Class CodesG11C 29/028 with adaption or trimming o...G11C 5/02 Disposition of storage elem...H03K 19/1737 using multiplexers H03K19/1...H03K 19/17728 Reconfigurable logic blocks...H03K 19/17744 for input/output signalsH03K 19/1776 for memoriesH10B 99/00 Subject matter not provided...
