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Full chip lithographic mask generation

  • US 10,146,124 B2
  • Filed: 02/23/2017
  • Issued: 12/04/2018
  • Est. Priority Date: 02/23/2016
  • Status: Active Grant
First Claim
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1. A method for full integrated circuit (IC) mask pattern generation, comprising:

  • generating, by a processor, an initial mask image from target polygons, wherein main feature polygons and SRAF image pixels are identified in the initial mask image;

    performing, by the processor using iterative optimization based on an inverse lithographic technology (ILT), a co-optimization on segments of main feature polygons and subresolution assist feature (SRAF) image pixels;

    after iterations of the co-optimization, determining SRAF polygons from the SRAF image pixels;

    determining optimized mask patterns by performing an edge based optimization on the segments of the main feature polygons and the SRAF polygons using gradient-based iterative optimization; and

    generating a full-IC mask based on the optimized mask patterns.

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