Full chip lithographic mask generation
First Claim
1. A method for full integrated circuit (IC) mask pattern generation, comprising:
- generating, by a processor, an initial mask image from target polygons, wherein main feature polygons and SRAF image pixels are identified in the initial mask image;
performing, by the processor using iterative optimization based on an inverse lithographic technology (ILT), a co-optimization on segments of main feature polygons and subresolution assist feature (SRAF) image pixels;
after iterations of the co-optimization, determining SRAF polygons from the SRAF image pixels;
determining optimized mask patterns by performing an edge based optimization on the segments of the main feature polygons and the SRAF polygons using gradient-based iterative optimization; and
generating a full-IC mask based on the optimized mask patterns.
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Abstract
A method, an apparatus, and a non-transitory computer readable medium for full chip mask pattern generation include: generating, by a processor, an initial mask image from target polygons, performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels, determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization, generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information, and generating optimized mask patterns based on a localized polygon optimization of the mask.
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Citations
20 Claims
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1. A method for full integrated circuit (IC) mask pattern generation, comprising:
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generating, by a processor, an initial mask image from target polygons, wherein main feature polygons and SRAF image pixels are identified in the initial mask image; performing, by the processor using iterative optimization based on an inverse lithographic technology (ILT), a co-optimization on segments of main feature polygons and subresolution assist feature (SRAF) image pixels; after iterations of the co-optimization, determining SRAF polygons from the SRAF image pixels; determining optimized mask patterns by performing an edge based optimization on the segments of the main feature polygons and the SRAF polygons using gradient-based iterative optimization; and generating a full-IC mask based on the optimized mask patterns. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An apparatus for full chip mask pattern generation, comprising:
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a memory; and a processor configured to execute instructions stored in the memory to; generate an initial mask image from target polygons, wherein main feature polygons and SRAF image pixels are identified in the initial mask image; perform, using iterative optimization based on an inverse lithographic technology (ILT) technique, a co-optimization on segments of main feature polygons and subresolution assist feature (SRAF) image pixels; after iterations of the co-optimization, determine SRAF polygons from the SRAF image pixels; determine optimized mask patterns by performing an edge based optimization on the segments of the main feature polygons and the SRAF polygons using an optical proximity correction (OPC) technique; generate a full-IC mask based on the optimized mask patterns. - View Dependent Claims (17, 18)
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19. A non-transitory computer readable medium for full chip mask pattern generation, having stored thereon executable instructions for causing a processor to perform the executable instructions to:
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perform, using iterative optimization based on an inverse lithographic technology (ILT) technique, a co-optimization on segments of main feature polygons and subresolution assist feature (SRAF) image pixels, wherein the main feature polygons and the SRAF image pixels are identified in an initial mask image generated from target polygons; after iterations of the co-optimization, determine SRAF polygons from the SRAF image pixels; determine optimized mask patterns by performing an edge based optimization on the segments of the main feature polygons and the SRAF polygons using an optical proximity correction (OPC) technique; enforce symmetrical placement of the SRAF polygons in the optimized mask patterns; and generate a full-IC mask based on the optimized mask patterns. - View Dependent Claims (20)
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Specification