Programming schemes for avoidance or recovery from cross-temperature read failures

• US 10,146,460 B1
• Filed: 09/27/2017
• Issued: 12/04/2018
• Est. Priority Date: 06/01/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Baum, Barak, Sagiv, Barak, Yogev, Einav, Gurgi, Eyal, Landau, Ariel
• Primary Examiner(s): Bashar, Mohammed A
• Application Number:
  US15/716,703
• Publication Number:
  US 20180349044A1
• Time in Patent Office: 433 Days
• CPC Class Codes: G06F 11/002 protecting against parasitic influences, e.g. noise, temperatures
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

Claims

1. A memory system, comprising:

an interface, configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values; and

storage circuitry configured to;

receive data for storage;

measure a temperature at a time of programming the received data; and

program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

2. The memory system according to claim 1, wherein the storage circuitry is configured to apply the second programming scheme by programming dummy bits to at least one or more identified memory cells that, when programmed using the first programming scheme, are estimated to be read erroneously if the temperature at reading time differs from the temperature at programming time.

3. The memory system according to claim 2, wherein the storage circuity is configured to identify in the received data one or more bit-locations corresponding to the identified memory cells, and to program the dummy bits only in the identified bit-locations.

4. The memory system according to claim 1, wherein the memory cells support storing data in multiple data pages having respective bit-significance values, and wherein the storage circuitry is configured to apply the second programming scheme by programming multiple instances of at least part of the received data, destined for storage in a data page of a given bit-significance value, in multiple respective groups of the memory cells.

5. The memory system according to claim 4, wherein the storage circuitry is configured to generate the multiple instances by encoding multiple respective partial subsets of the at least part of the received data using an Error Correction Code (ECC).

6. The memory system according to claim 1, wherein the storage circuitry is configured to apply the second programming scheme by identifying in the received data one or more bits at respective bit-locations corresponding to identified memory cells that, when programmed using the first programming scheme, are estimated to be read erroneously if the temperature at reading time is different from the temperature at programming time, to program the received data in a first word line of the memory cells, and to program in a second different word line of the memory cells auxiliary bits derived from the identified bits.

7. The memory system according to claim 6, wherein the storage circuity is configured to recover the received data from the first word line by reading the received data from the first word line, further reading the auxiliary bits from the second word line, and correcting the received data that was read from the first word line based on the auxiliary bits read from the second word line.

8. The memory system according to claim 6, wherein the storage circuitry is configured to derive the auxiliary bits by extracting a partial subset of the identified bits of the received data.

9. The memory system according to claim 6, wherein the storage circuitry is configured to derive the auxiliary bits by calculating one or more parity bits over the identified bits of the received data.

10. The memory system according to claim 1, wherein the memory cells are configured to store data using a predefined number of nominal programming levels of the analog voltages, and wherein the storage circuitry is configured to program the received data to the memory cells using a subset of the programming levels having a number of programming levels smaller than the predefined number.

11. A method for data storage, comprising:

in memory system comprising a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values, receiving data for storage;

measuring a temperature at a time of programming the received data; and

programing the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise programing the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

12. The method according to claim 11, wherein programming using the second programming scheme comprises programming dummy bits to at least one or more identified memory cells that, when programmed using the first programming scheme, are estimated to be read erroneously if the temperature at reading time differs from the temperature at programming time.

13. The method according to claim 12, and comprising identifying in the received data one or more bit-locations corresponding to the identified memory cells, wherein programming the dummy bits comprises programming the dummy bits only in the identified bit-locations.

14. The method according to claim 11, wherein the memory cells support storing data in multiple data pages having respective bit-significance values, and wherein programming using the second programming scheme comprises programming multiple instances of at least part of the received data, destined for storage in a data page of a given bit-significance value, in multiple respective groups of the memory cells.

15. The method according to claim 14, wherein programming the multiple instances comprises generating the multiple instances by encoding multiple respective partial subsets of the at least part of the received data using an Error Correction Code (ECC).

16. The method according to claim 11, wherein programming using the second programming scheme comprises identifying in the received data one or more bits at respective bit-locations corresponding to identified memory cells that, when programmed using the first programming scheme, are estimated to be read erroneously if the temperature at reading time is different from the temperature at programming time, programming the received data in a first word line of the memory cells, and programming in a second different word line of the memory cells auxiliary bits derived from the identified bits.

17. The method according to claim 16, and comprising recovering the received data from the first word line by reading the received data from the first word line, further reading the auxiliary bits from the second word line, and correcting the received data that was read from the first word line based on the auxiliary bits read from the second word line.

18. The method according to claim 16, wherein programming the auxiliary bits comprises deriving the auxiliary bits by extracting a partial subset of the identified bits of the received data.

19. The method according to claim 11, wherein the memory cells support storing data using a predefined number of nominal programming levels of the analog voltages, and wherein programming using the second programming scheme comprises programming the received data to the memory cells using a subset of the programming levels having a number of programming levels smaller than the predefined number.

20. The method according to claim 11, wherein the received data comprises at least a data page of a given bit-significance, wherein programing the received data using the second programming scheme comprises splitting bits of the data page into first and second groups and filling each of the first and second groups with all-ones bits up to a length of the data page, and programming the filled first and second groups to different respective first and second groups of the memory cells.