Synchronization logic for memory requests

• US 10,146,690 B2
• Filed: 06/13/2016
• Issued: 12/04/2018
• Est. Priority Date: 06/13/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sury, Samantika S., Blankenship, Robert G., Steely, Jr., Simon C.
• Primary Examiner(s): Lane, John A
• Application Number:
  US15/180,351
• Publication Number:
  US 20170357586A1
• Time in Patent Office: 904 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of cores; and

synchronization logic comprising circuitry, the circuitry to;

receive a first memory request and a second memory request;

determine whether the second memory request is in contention with the first memory request;

in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol; and

in response to a determination that the second memory request is not in contention with the first memory request, process the second memory request using a blocking cache coherence protocol.

2. The processor of claim 1, wherein:

the first memory request is received from a first core;

the second memory request is received from a second core;

the first memory request and the second memory request are in contention for a first memory address; and

at a time when the first memory request is received, the first memory address is cached in a third core.

3. The processor of claim 2, the circuitry further to:

send, to the third core, a blocking-protocol invalidation message associated with the first request; and

send, to the first core, a non-blocking-protocol invalidation message associated with the second request without waiting for a data response from the third core.

4. The processor of claim 3, the circuitry further to:

receive, from the third core, a data response associated with the first request; and

in response to a receipt of the data response from the third core, send, to the first core, a non-blocking-protocol acknowledgement message associated with the first request.

5. The processor of claim 4, the circuitry further to:

receive, from the first core, a data response associated with the second request; and

in response to a receipt of the data response from the first core, send, to the second core, a non-blocking-protocol acknowledgement message associated with the second request.

6. The processor of claim 4, the first core comprising cache logic implemented in circuitry, the cache logic of the first core to:

receive the non-blocking-protocol invalidation message associated with the second request; and

store the non-blocking-protocol invalidation message associated with the second request in a memory buffer of the cache logic until a receipt of the non-blocking-protocol acknowledgement message associated with the first request.

7. The processor of claim 6, the cache logic of the first core further to:

in response to a receipt of the non-blocking-protocol acknowledgement message associated with the first request;

process data included in the received non-blocking-protocol acknowledgement message to generate processed data;

send a data response including the processed data; and

process the stored non-blocking-protocol invalidation message to invalidate a local copy of the processed data.

8. A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:

receiving a first memory request from a first core of a processor;

receiving a second memory request from a second core of the processor;

in response to a determination that the second memory request is in contention with the first memory request, processing the second memory request using a non-blocking cache coherence protocol; and

in response to a determination that the second memory request is not in contention with the first memory request, processing the second memory request using a blocking cache coherence protocol.

9. The machine-readable medium of claim 8, wherein under the blocking cache coherence protocol, the second memory request is not processed until the first memory request is completed.

10. The machine-readable medium of claim 8, wherein the first memory request and the second memory request are in contention for a first memory address;

and

wherein, when the first memory request is received, the first memory address is cached in a third core.

11. The machine-readable medium of claim 10, wherein the method further comprises:

sending, to the third core, a blocking-protocol invalidation message associated with the first request; and

sending, to the first core, a non-blocking-protocol invalidation message associated with the second request without waiting for a data response from the third core.

12. The machine-readable medium of claim 11, wherein the method further comprises:

receiving, from the third core, a data response associated with the first request; and

in response to the data response from the third core, sending, to the first core, a non-blocking-protocol acknowledgement message associated with the first request.

13. The machine-readable medium of claim 12, wherein the method further comprises:

receiving, from the first core, a data response associated with the second request; and

in response to the data response from the first core, sending, to the second core, a non-blocking-protocol acknowledgement message associated with the second request.

14. A system comprising:

a processor comprising a plurality of cores and synchronization logic, the synchronization logic comprising circuitry to;

receive a first memory request and a second memory request;

determine whether the second memory request is in contention with the first memory request;

in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol; and

in response to a determination that the second memory request is not in contention with the first memory request, process the second memory request using a blocking cache coherence protocol; and

a system memory coupled to the processor.

15. The system of claim 14, wherein:

the first memory request is received from a first core;

the second memory request is received from a second core;

the first memory request and the second memory request are in contention for a first memory address; and

at a time when the first memory request is received, the first memory address is cached in a third core.

16. The system of claim 15, the circuitry further to:

send, to the third core, a blocking-protocol invalidation message associated with the first request; and

send, to the first core, a non-blocking-protocol invalidation message associated with the second request without waiting for a data response from the third core.

17. The system of claim 16, the circuitry further to:

receive, from the third core, a data response associated with the first request; and

in response to the data response from the third core, send, to the first core, a non-blocking-protocol acknowledgement message associated with the first request.

18. The system of claim 17, the first core comprising cache logic implemented in circuitry, the cache logic of the first core to:

receive the non-blocking-protocol invalidation message associated with the second request; and

store the non-blocking-protocol invalidation message associated with the second request in a buffer of the cache logic until a receipt of the non-blocking-protocol acknowledgement message associated with the first request.