Volatile/non-volatile memory device access provisioning system

• US 10,146,704 B2
• Filed: 02/16/2016
• Issued: 12/04/2018
• Est. Priority Date: 02/16/2016
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Masuyama, Jinsaku, Khatri, Mukund, Chao, Ching-Lung
• Primary Examiner(s): Mercado, Ramon A.
• Application Number:
  US15/044,871
• Publication Number:
  US 20170235682A1
• Time in Patent Office: 1,022 Days
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A volatile/non-volatile memory device access provisioning system includes a processing system and a controller coupled to a memory device. The controller provides an access key to the memory device and causes memory device communications to be passed to the processing system when the access key is available. The controller simply causes memory device communications to be passed to the processing system when the access key is not available. The memory device masks non-volatile memory subsystem access information in the memory device to prevent the processing system from accessing non-volatile memory subsystem(s) in the memory device, and then determines whether the access key has been received from the controller. The memory device will unmask the non-volatile memory subsystem access information such that the processing system can access non-volatile memory subsystem(s) in response to determining that the access key has been received from the controller.

Claims

1. A volatile/non-volatile memory device access provisioning system, comprising:

a first memory device connector;

a processing system that is coupled to the first memory device connector;

a first memory devise that is coupled to the first memory device connector, wherein the first memory device includes at least one volatile memory subsystem and at least one non-volatile memory subsystem; and

a controller that is coupled to the first memory device connector and that is configured to;

detect a first memory device in the first memory device connector;

determine whether an access key for the first memory device is available; and

provide, in response to determining that the access key for the first memory device is available, the access key to the first memory device; and

cause memory device communications to be passed to the processing system in response to determining that there are no other memory devices coupled to the controller, and

wherein the first memory device is configured to;

mask non-volatile memory subsystem access information that is included in the first memory device to prevent the processing system from accessing the at least one non-volatile memory subsystem, wherein the masking of the non-volatile memory subsystem access information prevents the processing system from being aware of the non-volatile memory subsystem;

determine the access key for the first memory device has been received from the controller; and

unmask the non-volatile memory subsystem access information such that the processing system can access the at least one non-volatile memory subsystem subsequent to the memory device communication being passed to the processing system.

2. The system of claim 1, wherein the controller is configured to:

cause memory device communications to be passed from the processing system to the controller in response to detecting system initialization.

3. The system of claim 1, wherein the access key for the first memory device includes a public key.

4. The system of claim 1, wherein the non-volatile memory subsystem access information includes Serial Presence Detect (SPD) access information.

5. The system of claim 1, further comprising:

a second memory device connector coupled to the controller; and

a second memory device that is coupled to the second memory device connector, wherein the second memory device includes at least one volatile memory subsystem and at least one non-volatile memory subsystem, and wherein the controller is configured to;

detect the second memory device in the second memory device connector;

determine an access key for the second memory device is unavailable; and

cause, in response to determining there are no other memory devices coupled to the controller, memory device communications to be passed to the processing system, wherein the second memory device is configured to;

mask non-volatile memory subsystem access information that is included in the second memory device to prevent the processing system from accessing the at least one non-volatile memory subsystem;

determine the access key for the second memory device has not been received from the controller; and

continue to mask the non-volatile memory subsystem access information that is included in the second memory device subsequent to memory device communications being passed to the processing system while providing access to the volatile memory subsystem.

6. The system of claim 1, wherein the masking the non-volatile memory subsystem access information includes at least one of:

overwriting the non-volatile memory subsystem access information, hiding a memory element that includes the non-volatile memory subsystem access information, and connecting a memory element to the first memory device connector that does not include the non-volatile memory subsystem access information.

7. The system of claim 1, wherein the non-volatile memory subsystem access information is associated with a purchased license to access the at least one non-volatile memory subsystem.

8. A method for provisioning access to a volatile/non-volatile memory device, comprising:

masking, by a memory device, non-volatile memory subsystem access information that is stored in the memory device in order to prevent a system that is coupled to the memory device via a memory device connector from accessing at least one non-volatile memory subsystem that is included in the memory device, wherein volatile memory subsystem access information that is stored in the memory device allows the system to access at least one volatile memory subsystem that is included in the memory device and wherein the masking of the non-volatile memory subsystems access information prevents the system from being aware of the non-volatile memory subsystem;

detecting, by a controller in the system, the memory device in a memory device connector;

determining, by the controller in the system, the valid access key for the memory device is available;

providing, by the controller in the system in response to determining that the valid access key for the memory device is available, the valid access key to the memory device;

determining, by the memory device, the valid access key has been received from the system;

unmasking, by the memory device, the non-volatile memory subsystem access information such that the system can access the at least one non-volatile memory subsystem in response to determining that the valid access key has been received from the system; and

causing memory device communications to be passed from the controller in the system to at least one processor in the system in response to determining that there are no other memory devices coupled to the controller.

9. The method of claim 8, further comprising:

causing, by the system, memory device communications to be passed from the at least one processor to the controller in response to detecting system initialization.

10. The method of claim 8, wherein determining whether the valid access key has been received from the system includes:

receiving, by the memory device, at least a portion of a public key from the system through the memory device connector; and

verifying, by the memory device, the at least the portion of the public key.

11. The method of claim 8, wherein the non-volatile memory subsystem access information includes Serial Presence Detect (SPD) access information.

12. The method of claim 8, wherein the at least one volatile memory subsystem includes a Dynamic Random Access Memory (DRAM) subsystem, and wherein the at least one non-volatile memory subsystem includes a flash memory subsystem.

13. The method of claim 8, wherein the masking the non-volatile memory subsystem access information includes at least one of:

overwriting the non-volatile memory subsystem access information, hiding a memory element that includes the non-volatile memory subsystem access information, and connecting a memory element to the memory device connector that does not include the non-volatile memory subsystem access information.