Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels

• US 10,147,651 B1
• Filed: 05/12/2017
• Issued: 12/04/2018
• Est. Priority Date: 05/12/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Xu, Peng, Yang, Jie
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US15/593,958
• Publication Number:
  US 20180331104A1
• Time in Patent Office: 571 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method of forming complementary vertical fins and vertical fins with uniform heights, including, forming a trench in a region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate, forming a reformed punch-through stop layer in a bottom portion of the trench, forming a fin formation region on the reformed punch-through stop layer, and forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region.

Claims

1. A method of forming complementary vertical fins with uniform heights, comprising:

forming a trench in a second region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate;

forming a reformed punch-through stop layer in a bottom portion of the trench;

forming a fin formation region on the reformed punch-through stop layer; and

forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region.

2. The method of claim 1, further comprising forming an isolation layer on the complementary vertical fin and the vertical fin;

and forming a first gate structure on the complementary vertical fin and a second gate structure on the vertical fin, wherein the complementary vertical fin forms a p-type fin field effect transistor, and the vertical fin forms an n-type fin field effect transistor.

3. The method of claim 1, wherein the trench has a depth in the range of about 50 nm to about 180 nm.

4. The method of claim 1, wherein the upper portion of the substrate has a thickness in the range of about 20 nm to about 80 nm.

5. The method of claim 1, wherein the vertical fins are silicon, and the complementary vertical fins are silicon-germanium.

6. The method of claim 1, wherein the fin formation region has a germanium (Ge) concentration in the range of about 10 at. % Ge to about 85 at. % Ge.

7. The method of claim 1, wherein the reformed punch-through stop layer includes arsenic or phosphorus to provide n-type doping.

8. The method of claim 1, wherein the vertical fins and complementary vertical fins are formed at the same time by a reactive ion etch (RIE).

9. The method of claim 1, wherein the vertical fins and complementary vertical fins have approximately the same height.

10. A method of forming complementary vertical fins with uniform heights, comprising:

forming a buried punch-through stop layer in a substrate, wherein the buried punch-through stop layer delineates an upper portion of the substrate from a lower portion of the substrate;

forming a trench in a second region of the substrate, wherein the trench extends through the upper portion of the substrate and buried punch-through stop layer, and extends into the lower portion of the substrate;

forming a reformed punch-through stop layer in the bottom portion of the trench;

forming a fin formation region on the reformed punch-through stop layer; and

forming complementary vertical fins from the fin formation region and vertical fins from the upper portion of the substrate on a first region of the substrate adjacent to the second region.

11. The method of claim 10, wherein the reformed punch-through stop layer includes arsenic or phosphorus to provide n-type doping.

12. The method of claim 11, wherein the fin formation region is silicon-germanium (SiGe) formed by epitaxial growth on the punch-through stop layer.

13. The method of claim 12, wherein the fin formation region has a germanium (Ge) concentration in the range of about 10 at. % Ge to about 85 at. % Ge.

14. The method of claim 12, wherein the reformed punch-through stop layer is thicker than the buried punch-through stop layer.

15. The method of claim 12, wherein the vertical fins are silicon, and the complementary vertical fins are silicon-germanium.