Process for fabricating a field effect transistor having a coating gate

• US 10,147,788 B2
• Filed: 10/12/2017
• Issued: 12/04/2018
• Est. Priority Date: 10/13/2016
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Augendre, Emmanuel, Coquand, Remi, Reboh, Shay
• Primary Examiner(s): Mehta, Ratisha
• Application Number:
  US15/782,105
• Publication Number:
  US 20180108733A1
• Time in Patent Office: 418 Days
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.

Claims

1. A process for fabricating a gate-wrap-around field-effect transistor, comprising:

providing a substrate surmounted with a superposition of first to third nanowires each having a median portion and first and second ends on either side of the median portion along a longitudinal axis thereof, each of the nanowires being made of a semiconductor, said second nanowire being disposed between the first and the third nanowires and being made of a semiconductor that is different from the semiconductor of the first nanowire and different from the semiconductor of the third nanowire, so that the first or the second nanowire is subjected to a mechanical strain along its longitudinal axis, the median portion of the first to third nanowires being covered by a sacrificial gate, electrical insulator being wrapped around a portion of the second nanowire intermediate between its median portion and its first end and between its median portion and its second end, the electrical insulator separating the first end from the median portion of the first and the third nanowires, and separating the second end from the median portion of the first and the third nanowires;

removing the first and the second ends of the first and the third nanowires selectively with respect to the first and the second ends of the second nanowire, so as to preserve the second nanowire to be continuous between its median portion and its first and second ends;

depositing a semiconductor that is different from that of the first to the third nanowires, by epitaxial growth from and around the first and the second ends of the second nanowire, so as to modify the mechanical strain in the median portion of the second nanowire;

then

removing the sacrificial gate, and removing the median portion of the first and the third nanowires; and

forming a gate electrode wrapped around the median portion of the second nanowire.

2. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, wherein the first to the third provided nanowires include silicon, and the first and the third nanowires including a proportion of germanium higher than that of the second nanowire.

3. The process for fabricating a gate-wrap-around field-effect transistor according to claim 2, wherein the first and the third provided nanowires are made of Si_(1-x)Ge_x, where 0.2<

x<

0.6.

4. The process for fabricating a gate-wrap-around field-effect transistor according to claim 2, wherein the deposited semiconductor is SiC doped in situ with phosphorus.

5. The process for fabricating a gate-wrap-around field-effect transistor according to claim 2, wherein the deposited semiconductor is SiGe doped in situ with boron.

6. The process for fabricating a gate-wrap-around field-effect transistor according to claim 5, wherein the deposited semiconductor has a germanium concentration higher than that of the first and the third nanowires.

7. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, wherein the second nanowire of the provided substrate is relaxed.

8. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, wherein the second nanowire of the provided substrate is tensile-strained along its longitudinal axis.

9. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, further comprising prior steps of:

removing intermediate portions of the first and the third initially continuous nanowires, between their first end and their median portion, and between their second end and their median portion; and

depositing the electrical insulator.

10. The process for fabricating a gate-wrap-around field-effect transistor according to claim 9, wherein the step of removing the intermediate portions of the first and the third nanowires comprises an implantation of ions into these intermediate portions and then a step of selectively etching these portions.

11. The process for fabricating a gate-wrap-around field-effect transistor according to claim 9, wherein the step of removing the intermediate portions of the first and the third nanowires comprises etching the intermediate portions of the first and the third nanowires according to their crystal planes.

12. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, further comprising a step of doping the second nanowire in a portion that is intermediate between its first end and its median portion and in a portion that is intermediate between its second end and its median portion, after the step of providing the substrate and before the step of removing the sacrificial gate.

13. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, wherein the first to the third provided nanowires have a thickness at most equal to 15 nm.

14. The process for fabricating a gate-wrap-around field-effect transistor according to claim 1, wherein the electrical insulator for the provided substrate has a thickness comprised between 3 nm and 15 nm between the first end and the median portion of the first and the third nanowires.