Process for fabricating vertically-aligned gallium arsenide semiconductor nanowire array of large area

• US 10,147,789 B2
• Filed: 06/25/2014
• Issued: 12/04/2018
• Est. Priority Date: 06/11/2014
• Status: Active Grant

• Current Assignee: Korea Research Institute of Standards and Science
• Original Assignee: Korea Research Institute of Standards and Science
• Inventors: Lee, Woo, Shin, Jeong Ho
• Primary Examiner(s): OLSEN, ALLAN W
• Application Number:
  US15/317,922
• Publication Number:
  US 20170125519A1
• Time in Patent Office: 1,623 Days
• Field of Search: None
• CPC Class Codes: B82B 3/00 Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
• CPC Class Codes: B82B 3/0014 Array or network of similar nanostructural elements
• CPC Class Codes: B82B 3/0019 without movable or flexible elements
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/30635 of AIIIBV compounds
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/819 III-As based compounds, e.g. AlxGayInzAs
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching

Abstract

The present invention relates to a method for manufacturing a GaAs semiconductor nanowire in a bottom-up type and, more particularly, to a method for manufacturing a vertically-aligned gallium arsenide semiconductor nanowire array in a large area by applying a voltage and a current from the outside using a metal thin film, which has been made through an economical method of fabricating a mesh-type metal thin film in a large area, as an anode such that holes (h⁺) are injected into a gallium arsenide substrate, thereby inducing a wet etching process continuously. The obtained vertically-aligned gallium arsenide semiconductor nanowire of a large area can be applied to fabrication of nanoelements, such as a solar cell, a transistor, and a light-emitting diode.

Claims

1. A method for fabricating a group III-V compound semiconductor nanowire array, comprising:

(a) preparing a patterned palladium containing metal mesh on a surface of a group III-V compound semiconductor substrate; and

(b) wet-etching the III-V compound semiconductor substrate contacting the metal mesh in an etchant by applying an external bias for electrochemical etching to the metal mesh, wherein a voltage or a current is applied to the metal mesh forming an anode and the substrate contacting the anode is etched which lowers the metal mesh, and wherein a portion of the substrate that does not contact the anode is not etched forming a mesh shape.

2. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein the metal mesh is formed of an alloy of two or more elements or is formed of two or more metals deposited as multiple layers.

3. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein a length of a nanowire is controlled by a time in which the wet-etching is performed or is controlled by a magnitude of the applied bias.

4. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein the etchant includes hydrofluoric acid (HF), hydrochloric acid (HCl), or nitric acid (HNO3).

5. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a nanowire is fabricated to be vertical to the substrate or is fabricated in a zigzag form.

6. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, the bias is applied to the substrate to induce a nanowire to have a porous surface.

7. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein in the wet-etching, a diameter of a nanowire is adjusted depending on a change in a size of a hole of the metal mesh.

8. The method for fabricating a group III-V compound semiconductor nanowire array of claim 1, wherein a group III-V compound semiconductor is a gallium arsenide.