System and method for monitoring and controlling parallel batteries

• US 10,148,099 B2
• Filed: 06/23/2016
• Issued: 12/04/2018
• Est. Priority Date: 07/01/2015
• Status: Active Grant

• Current Assignee: Carrier Corporation (Carrier Global Corporation)
• Original Assignee: Carrier Corporation (Carrier Global Corporation)
• Inventors: Kyllonen, Kimmo A., Seliski, John A.
• Primary Examiner(s): Tso, Edward
• Application Number:
  US15/191,179
• Publication Number:
  US 20170005492A1
• Time in Patent Office: 894 Days
• Field of Search: 320107, 320116, 320134, 320136, 320138, 320165
• CPC Class Codes: H02J 7/0024 Parallel/serial switching of connection of batteries to charge or load circuit
• CPC Class Codes: H02J 7/0034 using reverse polarity correcting or protecting circuits mechanical means of polarity protection H02J7/0045

Abstract

A power supply circuit is provided that includes first and second power sources coupled in parallel, a first circuit path that provides reverse current blocking and reverse polarity protection associated with positive terminals of the respective first and second power sources, a second circuit path that bypasses current blocking of the first circuit path, a third circuit path that provides reverse polarity protection associated with negative terminals of the respective first and second power sources, and a bypass control circuit that controls the second circuit path based on determination of a predetermined condition.

Claims

1. A power supply circuit, comprising:

first and second power sources coupled in parallel;

a first circuit path that provides reverse current blocking and reverse polarity protection associated with positive terminals of the respective first and second power sources, the first circuit path including a first transistor to provide reverse polarity protection for output from the positive terminal of the first power source by a first body diode of the first transistor, and a second transistor to provide reverse polarity protection for output from the positive terminal of the second power source by a second body diode of the second transistor;

a second circuit path that bypasses current blocking of the first circuit path, the second circuit path including a first bypass channel of the first transistor, and a second bypass channel of the second transistor;

a third circuit path that provides reverse polarity protection associated with negative terminals of the respective first and second power sources, the third circuit path including a third transistor to provide reverse polarity protection by a third body diode of the third transistor for output from the negative terminal of the first power source, and a fourth transistor to provide reverse polarity protection by a fourth body diode of the fourth transistor for output from the negative terminal of the second power source; and

a bypass control circuit that controls the second circuit path based on determination of a predetermined condition.

2. The power supply circuit of claim 1, wherein the bypass control circuit includes:

a first control transistor that controls the first bypass channel, wherein when the first bypass channel is turned on, output from the first power source flows through the first bypass channel instead of through a first body diode, and when the first bypass channel is turned off, output from the first power source undergoes reverse current blocking and reverse polarity protection by the first body diode; and

a second control transistor that controls the second bypass channel, wherein when the second bypass channel is turned on, output from the second power source flows through the second bypass channel instead of through the second body diode, and when the second bypass channel is turned off, output from the second power source undergoes reverse current blocking and reverse polarity protection by the second body diode.

3. The power supply circuit of claim 2, wherein the bypass control circuit further includes a controller that transmits control signals to the first and second control transistors to control the first and second bypass channels independently of one another.

4. The power supply circuit of claim 3, wherein the controller controls turning off at least one of the first and second bypass channels for a predetermined time interval, the predetermined time interval defining a power up phase of either of the first and second power sources.

5. The power supply circuit of claim 3, wherein the controller controls turning off at least one of the first and second bypass channels in response to detection of installation with proper polarity orientation of one of the first and second power sources, so that the output from at least one of the first and second power sources flows through the first circuit path, but not through the second circuit path.

6. The power supply circuit of claim 5, wherein the controller monitors terminal voltages of the first and second power sources in response to detection of installation with proper polarity orientation of at least one of the first and second power sources.

7. The power supply circuit of claim 5, wherein the controller controls turning on at least one of the first and second bypass channels in response to a determination that a differential voltage between the terminal voltages of the first and second power sources is below a predetermined threshold, so that the output from at least one of the first and second power sources flows through the second circuit path, but not through the first circuit path.

8. The power supply circuit of claim 5, wherein the controller controls turning off at least one of one of the first and second bypass channels upon a determination that the differential voltage is above the predetermined threshold.

9. The power supply circuit of claim 1, further comprising a Schottky diode connected in parallel to the first transistor to provide reverse current blocking and reverse polarity protection.

10. The power supply circuit of claim 1, wherein the first and second transistors are enhancement-mode P-channel MOSFETs, and the third and fourth transistors are enhancement-mode N-channel MOSFETs.

11. A power supply circuit, comprising:

a power source;

a first circuit path that provides reverse current blocking and reverse polarity protection associated with a positive terminal of the power source, the first circuit path including a first transistor to provide reverse polarity protection for output from the positive terminal of the power source by a first body diode of the first transistor;

a second circuit path that bypasses current blocking of the first circuit path, the second circuit path including a bypass channel of the first transistor;

a third circuit path that provides reverse polarity protection associated with a negative terminals of the power source, the third path including a second transistor to provide reverse polarity protection by a second body diode of the second transistor for output from the negative terminal of the power source; and

a bypass control circuit that controls the first and second circuit paths based on determination of a predetermined condition.

12. The power supply circuit of claim 11, wherein the bypass control circuit includes a control transistor that controls the bypass channel of the first transistor, so that when the bypass channel is turned on, output from the power source flows through the bypass channel instead of through the first body diode;

and when the bypass channel is turned off, output from the power source undergoes reverse current blocking and reverse polarity protection by the first body diode.

13. The power supply circuit of claim 11, further comprising a controller that controls turning off at least one of the first and second bypass channels for a predetermined time interval, the predetermined time interval defining a power up phase of either of the first and second power sources.

14. A method of protecting a power supply circuit comprising:

controlling a first and second circuit path, comprising;

providing reverse current blocking and reverse polarity protection associated with positive terminals of respective first and second power sources;

bypassing current blocking of the first circuit path in a second circuit path;

providing reverse polarity protection associated with negative terminals of the respective first and second power sources;

controlling the second circuit path based on determination of a predetermined condition;

controlling a first bypass channel of a first transistor, wherein when the first bypass channel is turned on, output from the first power source flows through the first bypass channel instead of through a first body diode of the first transistor, and when the first bypass channel is turned off, output from the first power source undergoes reverse current blocking and reverse polarity protection by the first body diode; and

controlling a second bypass channel of a second transistor, wherein when the second bypass channel is turned on, output from the second power source flows through the second bypass channel instead of through a second body diode of the second transistor, and when the second bypass channel is turned off, output from the second power source undergoes reverse current blocking and reverse polarity protection by the second body diode.

15. The method of claim 14, wherein the first and second bypass channels are controlled independently of one another.

16. The method of claim 15 further comprising controlling turning off at least one of the first and second bypass channels in response to detection of installation with proper polarity orientation of one of the first and second power sources, so that the output from at least one of the first and second power sources flows through the first circuit path, but not through the second circuit path.

17. The method of claim 16 further comprising monitoring terminal voltages of the first and second power sources in response to detection of installation with proper polarity orientation of at least one of the first and second power sources.

18. The method of claim 17 further comprising controlling turning on at least one of the first and second bypass channels in response to a determination that a differential voltage between the terminal voltages of the first and second power sources is below a predetermined threshold, so that the output from at least one of the first and second power sources flows through the second circuit path, but not through the first circuit path.

19. The method of claim 18 further comprising controlling turning off at least one of one of the first and second bypass channels upon a determination that the differential voltage is above the predetermined threshold.

20. The method of claim 14, further comprising controlling turning off at least one of the first and second bypass channels for a predetermined time interval, the predetermined time interval defining a power up phase of either of the first and second power sources.