Configurable computing array die based on printed memory and two-sided integration
First Claim
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1. A configurable computing array die, comprising:
- a semiconductor substrate having a first side and a second side;
at least a configurable computing element formed on said first side, said configurable computing element comprising;
a first printed array for storing a first look-up table (LUT) of a first basic function;
a second printed array for storing a second LUT of a second basic function;
a plurality of internal configurable interconnects coupling said first and second printed arrays;
wherein said configurable computing element selectively realizes said first or second basic function by programming said internal configurable interconnects;
at least a configurable logic element formed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element;
wherein said configurable computing array die realizes a complex math function by programming said configurable computing element and said configurable logic element.
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Abstract
The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.
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Citations
20 Claims
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1. A configurable computing array die, comprising:
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a semiconductor substrate having a first side and a second side; at least a configurable computing element formed on said first side, said configurable computing element comprising; a first printed array for storing a first look-up table (LUT) of a first basic function; a second printed array for storing a second LUT of a second basic function; a plurality of internal configurable interconnects coupling said first and second printed arrays; wherein said configurable computing element selectively realizes said first or second basic function by programming said internal configurable interconnects; at least a configurable logic element formed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element; wherein said configurable computing array die realizes a complex math function by programming said configurable computing element and said configurable logic element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A configurable computing array die, comprising:
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a semiconductor substrate having a first side and a second side; at least a configurable computing element formed on said first side, said configurable computing element comprising; a first printed array for storing a first look-up table (LUT) of a first basic function; a second printed array for storing a second LUT of a second basic function; a plurality of internal configurable interconnects coupling said first and second printed arrays; wherein said configurable computing element selectively realizes said first or second basic function by programming said internal configurable interconnects; at least a configurable logic element formed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element; at least a configurable interconnect for selectively realizing an interconnect from an interconnect library; wherein said configurable computing array die realizes a complex math function by programming said configurable computing element, said configurable logic element and said configurable interconnect. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification