Load reduced memory module

• US 10,149,383 B2
• Filed: 11/15/2017
• Issued: 12/04/2018
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/814,180
• Publication Number:
  US 20180139843A1
• Time in Patent Office: 384 Days
• Field of Search: 365 63
• CPC Class Codes: G06F 1/184 Mounting of motherboards
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7803 System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/11 Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10189 Non-printed connector

Abstract

The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Claims

1. A memory module comprising:

a plurality of device sites, wherein each device site of the plurality of device sites is a location at which at least one memory device is disposed;

a first chip select (CS) pin to receive a first CS signal from a memory controller;

a second CS pin to receive a second CS signal from a second memory module;

a buffer component coupled to the first CS pin and the second CS pin, wherein the buffer component is to;

select a first set of one or more sites of the plurality of device sites using a third CS signal when the first CS signal is received on the first CS pin from the memory controller; and

select a second set of one or more sites of the plurality of device sites using a fourth CS signal when the second CS signal is received on the second CS pin from the second memory module.

2. The memory module of claim 1, further comprising

a third CS pin to receive a fifth CS signal from a third memory module, wherein the buffer component is to select a third set of one or more sites of the plurality of device sites using a sixth CS signal when the fifth CS signal is received on the third CS pin.

3. The memory module of claim 1, wherein the buffer component comprises:

a pair of flip-flops coupled between the first CS pin and the first set of one or more sites of the plurality of device sites; and

a single flip-flop coupled between the second CS pin and the second set of one or more sites of the plurality of device sites.

4. The memory module of claim 1, wherein the buffer component comprises:

a first flip-flop coupled to the first CS pin;

a second flip-flop coupled to an output of the first flip-flop, wherein an output of the second flip-flop is coupled to the first set of one or more sites of the plurality of device sites; and

a third flip-flop coupled to the second CS pin, wherein an output of the third flip-flop is coupled to the second set of one or more sites of the plurality of device sites.

5. The memory module of claim 4, wherein the buffer component further comprises:

an input buffer coupled between the second CS pin and the third flip-flop; and

an output buffer coupled to the output of the first flip-flop and the second CS pin.

6. The memory module of claim 5, wherein the output buffer is to output a copy of the first CS signal on the second CS pin when the first CS signal is output from the first flip-flop.

7. The memory module of claim 4, further comprising

a clock pin to receive a clock signal, wherein the buffer component further comprises a phase locked loop (PLL) coupled to the clock pin, wherein an output of the PLL is coupled to a clock input of the first flip-flop, a clock input of the second flip-flop, and a clock input of the third flip-flop.

8. The memory module of claim 1, wherein the buffer component is to output a copy of the first CS signal on the second CS pin when the first CS signal is received on the first CS pin.

9. The memory module of claim 1, wherein each device site of the plurality of device sites comprises at least one of a single memory die, a package stack of at least two memory dies, or a die stack of at least two memory dies.

10. The memory module of claim 1, wherein each device site of the plurality of device sites comprises a double data rate fourth generation (DDR4) dynamic random-access memory (DRAM) device.

11. The memory module of claim 10, wherein the DDR4 DRAM device comprises:

an array;

a data path coupled to the array;

a primary port coupled to the data path;

a secondary port coupled to the data path; and

a command decoder coupled to the array, the data path, and the buffer component.

12. The memory module of claim 1, further comprising

a data buffer component coupled to one or more site of the plurality of device sites.

13. The memory module of claim 12, wherein the data buffer component comprises:

a multiplexer coupled to a plurality of input ports;

control logic coupled to the multiplexer; and

a synchronizer coupled to the control logic and the multiplexer.

14. The memory module of claim 1, further comprising

a plurality of data buffer components, wherein each data buffer component of the plurality of data buffer components is coupled to at least two device sites of the plurality of device sites.

15. A memory module comprising:

a circuit board comprising a plurality of device sites, wherein each device site of the plurality of device sites is a location on the circuit board at which at least one respective memory device is disposed, wherein the circuit board further comprises;

a first pin to receive a first select (CS) signal from a memory controller;

a second pin to receive a second CS signal from a second memory module;

means for selecting a first set of one or more sites of the plurality of device sites when the first CS signal is received at the first pin; and

means for selecting a second set of one or more sites of the plurality of device sites when the second CS signal is received at the second pin.

16. The memory module of claim 15, further comprising means for receiving a third CS signal from a third memory module.

17. The memory module of claim 15, further comprising

means for sending a copy of the first CS signal to the second memory module.

18. A memory module comprising:

a plurality of memory devices;

a first pin;

a second pin; and

a command and address (CA) buffer component coupled to the first pin, the second pin, and the plurality of memory devices, wherein the CA buffer component comprises;

a first flip-flop coupled to the first pin;

a second flip-flop coupled to an output of the first flip-flop, wherein an output of the second flip-flop is coupled to a first subset of the plurality of memory devices; and

a third flip-flop coupled to the second pin, wherein an output of the third flip-flop is coupled to a second subset of the plurality of memory devices, wherein memory devices in the second subset are not part of the first subset.

19. The memory module of claim 18, wherein the CA buffer component further comprises:

an input buffer coupled between the second pin and the third flip-flop; and

an output buffer coupled to the output of the first flip-flop and the second pin.

20. The memory module of claim 18, further comprising

a third pin, wherein the CA buffer component further comprises a phase locked loop (PLL) coupled to the third pin, wherein an output of the PLL is coupled to a clock input of the first flip-flop, a clock input of the second flip-flop, and a clock input of the third flip-flop.