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Load reduced memory module

  • US 10,149,383 B2
  • Filed: 11/15/2017
  • Issued: 12/04/2018
  • Est. Priority Date: 10/15/2013
  • Status: Active Grant
First Claim
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1. A memory module comprising:

  • a plurality of device sites, wherein each device site of the plurality of device sites is a location at which at least one memory device is disposed;

    a first chip select (CS) pin to receive a first CS signal from a memory controller;

    a second CS pin to receive a second CS signal from a second memory module;

    a buffer component coupled to the first CS pin and the second CS pin, wherein the buffer component is to;

    select a first set of one or more sites of the plurality of device sites using a third CS signal when the first CS signal is received on the first CS pin from the memory controller; and

    select a second set of one or more sites of the plurality of device sites using a fourth CS signal when the second CS signal is received on the second CS pin from the second memory module.

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