Recovering stranded data

• US 10,152,399 B2
• Filed: 07/30/2013
• Issued: 12/11/2018
• Est. Priority Date: 07/30/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Wheeler, Andrew R., Lesartre, Gregg B.
• Primary Examiner(s): Kudirka, Joseph R
• Application Number:
  US14/888,338
• Publication Number:
  US 20160132413A1
• Time in Patent Office: 1,960 Days
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/203 using migration
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile memory (NVM) in a home node over a sideband interface and writing the data to a target memory region, wherein the target memory region is in a fail-over node.

Claims

1. A method for recovering stranded data, comprising:

in response to detecting a failure of a home node, copying data from a non-volatile memory (NVM) in the home node over a sideband interface across a sideband bus interconnecting a management device of the home node to a management device of a fail-over node; and

writing the data to a target memory region, wherein the target memory region is in the fail-over node.

2. The method of claim 1, further comprising writing the data to a second NVM in the fail-over node.

3. The method of claim 1, further comprising writing the data to a virtual memory area in the fail-over node.

4. The method of claim 1, further comprising accessing the NVM in the home node from a management subsystem.

5. The method of claim 1, further comprising accessing the NVM when main system power is off to the home node.

6. The method of claim 1, further comprising providing a backup power in case all power has failed in the home node.

7. The method of claim 1, further comprising reactivating processes in the target memory region.

8. The method of claim 1, further comprising:

migrating a plurality of memory stripes from a corresponding plurality of NVMs in the home node to the fail-over node;

detecting if any of the plurality of memory stripes comprises missing or defective data; and

rebuilding the missing or defective data.

9. The method of claim 1, wherein the writing of the data to the target memory region in the fail-over node is through a system management device of the fail-over node.

10. The method of claim 1, wherein the sideband interface comprises a serial presence detect interface.

11. The method of claim 1 further comprising:

prior to the failure of the home node, accessing data in the nonvolatile memory in the home node via a memory controller, wherein the copying of the data from the non-volatile memory (NVM) in the home node over the sideband interface across the sideband bus interconnecting bus interconnecting the management device of the home node to the management device of the failover node is independent of the memory controller.

12. The method of claim 1, wherein the management device of the home node resides on a dual in-line memory module (DIMM).

13. The method of claim 12, wherein the DIMM further comprises volatile memory, a nonvolatile memory controller for controlling the NVM, and a DIMM controller for reading and writing data to the volatile memory, wherein the copying of the data from the NVM in the home node over the sideband interface across the sideband bus interconnecting the management device of the home node to the management device of the fail-over node further comprises propagating the data being copied from the nonvolatile memory in the home node across the nonvolatile memory controller and across the DIMM controller.

14. The method of claim 1, wherein the sideband bus comprises a system management bus of a management network through which communications from a management system are communicated.

15. A computing system, comprising:

a home node, comprising;

a processor;

a memory controller coupled to the processor of the home node;

a main network interface coupled to the processor of the home node, and a network;

a non-volatile memory (NVM) coupled to the memory controller of the home node; and

a system management device, coupled to the memory controller of the home node, the processor of the home node, and a system management network;

a fail-over node, comprising;

a processor;

a memory controller coupled to the processor of the fail-over node;

a main network interface coupled to the processor of the fail-over node, and to the network;

a target memory region coupled to the memory controller of the fail-over node; and

a system management device, coupled to the memory controller of the fail-over node, the processor of the fail-over node, and the system management network; and

a system management processor provided in the system management device of the fail-over node or another system device connected to the home node across the system management network, wherein the system management processor is to access data stored in the NVM of the home node through the system management device in the home node, and transfer the data to the target memory region of the fail-over node through the system management device of the fail-over node across the system management network.

16. The computing system of claim 15, wherein the system management device in the home node detects a failure in the home node prior to transferring the data from the NVM of the home node to the target memory region.

17. The computing system of claim 15, wherein the system management device in the home node comprises a back-up power driver to power the memory controller in case of a complete failure of system power in the home node.

18. The computing system of claim 15, wherein the system management device in the home node comprises:

a processor; and

a memory comprising instructions, wherein the instructions;

direct the processor of the system management device in the home node to detect a failure of the home node;

access the data in the NVM; and

transfer the data to a target memory region in the fail-over node.

19. The computing system of claim 15, wherein the system management network comprises a management server that monitors operation of a plurality of nodes and identifies a fail-over node for any of a plurality of nodes that fail.

20. The computing system of claim 15, wherein the system management processor is to access the data stored in the NVM of the home node over a sideband management bus connecting the system management device in the home node and the system management device in the fail-over node.

21. The computing system of claim 20, wherein the sideband management bus comprises a serial presence detect interface.

22. A tangible, non-transitory, machine-readable medium comprising instructions to direct a processor to:

detect a failure of a home node;

access data in a non-volatile memory (NVM) of the home node over a sideband management bus of a management device of a memory controller in response to the failure of the home node being detected; and

transfer the data across the sideband management bus to a target memory region in a fail-over node.

23. The tangible, non-transitory, machine-readable medium of claim 22, comprising instructions to reactivate processes in the fail-over node.

24. The tangible, non-transitory, machine-readable medium of claim 22, wherein the sideband management bus is connected to the management device of the memory controller by a serial presence detect interface.