Coherent controller

• US 10,152,435 B2
• Filed: 02/02/2017
• Issued: 12/11/2018
• Est. Priority Date: 06/20/2016
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Bandic, Zvonimir Z., Cargnini, Luis Vitorio, Vucinic, Dejan, Wang, Qingbo
• Primary Examiner(s): Nam, Hyun
• Application Number:
  US15/423,205
• Publication Number:
  US 20170364459A1
• Time in Patent Office: 677 Days
• Field of Search: None
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells

Abstract

A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

Claims

1. A system comprising:

a bus;

at least one processor coupled to the bus; and

a storage device coupled to the bus, the storage device comprising;

storage class memory;

a buffer; and

a controller configured to;

receive an instruction to provide data to the bus; and

responsive to receiving the instruction to provide data to the bus;

retrieve data from the storage class memory;

update the buffer to represent the data retrieved from the storage class memory; and

output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer,

wherein the at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

2. The system of claim 1, wherein the bus comprises a coherence bus.

3. The system of claim 1, wherein the controller is further configured to perform wear leveling of the storage class memory.

4. The system of claim 1, wherein the controller is further configured to perform error correction of data after retrieving the data from the storage class memory and prior to updating the buffer to represent the data.

5. The system of claim 1, wherein the controller is further configured to control access rights to data stored in the storage class memory.

6. The system of claim 1, wherein the storage class memory comprises at least one of phase change memory or resistive random-access memory.

7. The system of claim 1, wherein:

the storage device further comprises a register configured to store instructions for accessing data stored at the buffer; and

wherein the controller is further configured to receive the instruction to provide data to the bus via the register.

8. A method comprising:

receiving, by a coherent controller, an instruction to provide data to a coherence bus, wherein at least one processor is coupled to the coherence bus; and

responsive to receiving the instruction to provide data to the coherence bus;

fetching, by the coherent controller, data from storage class memory;

updating, by the coherent controller, a buffer to represent the data fetched from the storage class memory; and

writing, by the coherent controller, at the coherence bus, an indication that data responsive to the instruction to provide data to the coherence bus is available at the buffer,

wherein the at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the coherence bus after the coherent controller receives the instruction to provide data to the coherence bus and before the coherent controller writes the indication.

9. The method of claim 8, further comprising:

performing, by the coherent controller, wear leveling of the storage class memory.

10. The method of claim 8, further comprising:

performing, by the coherent controller, error correction of data after retrieving the data from the storage class memory and prior to updating the buffer to represent the data.

11. The method of claim 8, further comprising:

controlling, by the coherent controller, access rights to data stored in the storage class memory.

12. The method of claim 8, wherein the storage class memory comprises at least one of phase change memory or resistive random-access memory.

13. The method of claim 8, further comprising:

receiving, by the coherent controller, the instruction to provide data to the coherence bus via a register.

14. A non-transitory computer-readable storage medium encoded with instructions that, when executed, cause a controller to:

receive an instruction to provide data to a bus, wherein at least one processor is coupled to the bus; and

responsive to receiving the instruction to provide data to the bus;

retrieve data from a storage class memory;

update a buffer to represent the data retrieved from the storage class memory; and

output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer,

wherein the at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

15. The non-transitory computer-readable storage medium of claim 14, wherein the bus comprises a coherence bus.

16. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further cause the controller to perform wear leveling of the storage class memory.

17. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further cause the controller to perform error correction of data after retrieving the data from the storage class memory and prior to updating the buffer to represent the data.

18. The non-transitory computer-readable storage medium of claim 14, wherein the instructions further cause the controller to control access rights to data stored in the storage class memory.

19. The non-transitory computer-readable storage medium of claim 15, wherein the storage class memory comprises at least one of phase change memory or resistive random-access memory.

20. A system comprising:

means for receiving an instruction to provide data to a bus;

means for retrieving data from storage class memory in response to receiving the instruction to provide data to the bus;

means for updating a buffer to represent the data retrieved from the storage class memory in response to receiving the instruction to provide data to the bus; and

means for outputting at the bus an indication that data responsive to the instruction to provide data to the bus is available at the buffer in response to receiving the instruction to provide data to the bus,

wherein at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

21. The system of claim 20, further comprising:

means for performing wear leveling of the storage class memory.

22. The system of claim 20, further comprising:

means for performing error correction of data after retrieving the data from the storage class memory and prior to updating the buffer to represent the data.

23. The system of claim 20, further comprising:

means for controlling access rights to data stored in the storage class memory.

24. The system of claim 20, further comprising:

means for receiving the instruction to provide data to the bus via a register.