Non-volatile memory with backing up of programmed data

• US 10,153,046 B1
• Filed: 10/30/2017
• Issued: 12/11/2018
• Est. Priority Date: 10/30/2017
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Agarwal, Dinesh, Golechchha, Hitesh
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/798,009
• Time in Patent Office: 407 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory system comprises a plurality of non-volatile memory cells grouped into blocks of memory cells and a control circuit in communication with the memory cells. The control circuit is configured to program original data to a first block of memory cells and backup the original data by programming a copy of the original data across multiple blocks of memory cells at a word line offset. After being used to store backups of original data, blocks are rotated to be used for storing original data.

Claims

1. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells grouped into blocks of memory cells; and

a control circuit in communication with the memory cells, the control circuit configured to program first data to a first block of memory cells and program a copy of the first data across second and third blocks of memory cells such that a first portion of the copy of the first data is programmed into the second block and a second portion of the copy of the first data is programmed into the third block.

2. The non-volatile storage apparatus of claim 1, wherein:

the first data is grouped into pages of data;

the copy of the first data is grouped into pages of copied data; and

the control circuit is configured to program the copy of the first data to the second block and the third block such that pages of copied data in the second block and pages of copied data in the third block are at a word line offset in comparison to corresponding pages of data in the first block.

3. The non-volatile storage apparatus of claim 1, wherein:

the control circuit is configured to program the copy of the first data across second and third blocks of memory cells such the copy of first data is immediately adjacent to a copy of other second data with no intervening pseudo data between the copy of first data and the copy of other second data.

4. The non-volatile storage apparatus of claim 1, wherein:

the control circuit is configured to program the copy of the first data across second and third blocks of memory cells such that a first half of the copy of the first data is programmed into the second block and a second half of the copy of the first data is programmed into the third block.

5. The non-volatile storage apparatus of claim 1, wherein:

the first portion of the copy of the first data is stored contiguously in the second block and the second portion of the copy of the first data is stored contiguously in the third block.

6. The non-volatile storage apparatus of claim 1, wherein:

the control circuit configured to program second data to a fourth block of memory cells and program a copy of the second data across the third block and a fifth block of memory cells such that a first portion of the copy of the second data is programmed into the third block and a second portion of the copy of the second data is programmed into the fifth block.

7. The non-volatile storage apparatus of claim 6, wherein:

the control circuit configured to confirm successful programming of the first data in the first block of memory cells and the second data in the fourth block of memory cells; and

the control circuit configured to release and erase the third block of memory cells in response to successful programming of the first data in the first block of memory cells and the second data in the fourth block of memory cells.

8. The non-volatile storage apparatus of claim 7, wherein:

the control circuit configured to use the released third block of memory cells to store third data and to temporarily backup the third data in other blocks of memory cells.

9. The non-volatile storage apparatus of claim 1, wherein:

the control circuit is configured to determine that the programming of the first data in the first block of memory cells is unsuccessful; and

in response to determining that the programming of the first data in the first block of memory cells is unsuccessful, the control circuit is configured to recover a first subset of the first data from the first block and a second subset of the first data from either the second block or the third block.

10. The non-volatile storage apparatus of claim 1, wherein:

the control circuit is configured to determine that the programming of the first data in the first block of memory cells is unsuccessful; and

in response to determining that the programming of the first data in the first block of memory cells is unsuccessful, the control circuit is configured to recover at least a subset of the first data from either the second block or the third block.

11. The non-volatile storage apparatus of claim 1, wherein:

the control circuit is configured to program the first data to the first block of memory cells as one bit per memory cell;

the control circuit is further configured to program additional data to additional blocks of memory cells as one bit per memory cell and program copies of the additional data to other blocks of memory cells; and

the control circuit is further configured to combine the first data from the first block of memory cells with the additional data from the additional blocks of memory cells as multiple bits per memory cell and store that combined data as multiple bits per memory cell in a target block of memory cells.

12. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells form multiple planes, each plane includes multiple blocks of memory cells; and

the control circuit is configured to concurrently erase blocks of memory cells from different planes that are storing copies of data all of which has been confirmed to have been programmed successfully into other target blocks.

13. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells form three dimensional memory arrays on multiple memory die; and

the control circuit includes a controller that is separate from, and connected to, the multiple memory die.

14. An apparatus, comprising:

a control circuit configured to communicate with a plurality of non-volatile memory cells grouped into blocks of memory cells, the control circuit configured to program first data to a first block of memory cells and program a copy of the first data across second and third blocks of memory cells such that a first portion of the copy of the first data is programmed into the second block and a second portion of the copy of the first data is programmed into the third block.

15. The apparatus of claim 14, wherein:

the first data is grouped into pages of data;

the copy of the first data is grouped into pages of copied data; and

the control circuit is configured to program the copy of the first data to the second block and the third block such that pages of copied data in the second block and pages of copied data in the third block are at a word line offset in comparison to corresponding pages of data in the first block.

16. The apparatus of claim 14, wherein:

the control circuit is configured to program second data to a fourth block of memory cells and program a copy of the second data across the third block and a fifth block of memory cells such that a first portion of the copy of the second data is programmed into the third block and a second portion of the copy of the second data is programmed into the fifth block.

17. The apparatus of claim 16, wherein:

the control circuit is configured to confirm successful programming of the first data in the first block of memory cells and the second data in the fourth block of memory cells; and

the control circuit is configured to release and erase the third block of memory cells in response to successful programming of the first data in the first block of memory cells and the second data in the fourth block of memory cells.

18. An apparatus, comprising:

a memory interface configured to communicate with a plurality of non-volatile memory cells grouped into blocks of memory cells; and

one or more processors configured to communicate with the memory cells using the memory interface, the one or more processors configured to program first data to a first block of memory cells and program a copy of the first data across second and third blocks of memory cells such that a first portion of the copy of the first data is programmed into the second block and a second portion of the copy of the first data is programmed into the third block.

19. The apparatus of claim 18, wherein:

the first data is grouped into pages of data;

the copy of the first data is grouped into pages of copied data; and

the one or more processors are configured to program the copy of the first data to the second block and the third block such that pages of copied data in the second block and pages of copied data in the third block are at a word line offset in comparison to corresponding pages of data in the first block.