Semiconductor structure

• US 10,153,353 B1
• Filed: 06/05/2017
• Issued: 12/11/2018
• Est. Priority Date: 06/05/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liou, En-Chiuan, Tung, Yu-Cheng, Lee, Rung-Yuan, Yang, Chih-Wei
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US15/613,278
• Publication Number:
  US 20180350934A1
• Time in Patent Office: 554 Days
• Field of Search: None
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

Claims

1. A semiconductor structure, comprising:

a substrate, having an interlayer dielectric (ILD) disposed thereon;

a first gate structure, disposed in the ILD, wherein the first gate structure comprises a gate electrode and two inward curving spacers disposed on two sides of the gate electrode, and the gate electrode has four inward curving sidewalls; and

a second gate structure disposed in the ILD, wherein the second gate structure comprises a second gate electrode and two outward curving spacers disposed on two sides of the gate electrode.

2. The semiconductor structure of claim 1, wherein each inward curving spacer comprises a top point and a bottom point defined at the topmost portion and at the bottommost portion of the inward curving spacer respectively, and a central point defined at the central portion of the inward curving spacer.

3. The semiconductor structure of claim 2, wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two top points of the two inward curving spacers.

4. The semiconductor structure of claim 2, wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two bottom points of the two inward curving spacers.

5. The semiconductor structure of claim 1, wherein the first gate structure is an N-type metal oxide semiconductor field effect transistor (NMOSFET).

6. The semiconductor structure of claim 1, wherein the second gate structure is a P-type metal oxide semiconductor field effect transistor (PMOSFET).

7. A semiconductor structure, comprising:

a substrate, having an interlayer dielectric (ILD) disposed thereon;

a first gate structure, disposed in the ILD, wherein the first gate structure comprises a gate electrode and two inward curving spacers disposed on two sides of the gate electrode, and the gate electrode has four inward curving sidewalls, and wherein the gate electrode is inwardly curved at narrowest width at a middle section thereof.

8. The semiconductor structure of claim 7, wherein each inward curving spacer comprises a top point and a bottom point defined at the topmost portion and at the bottommost portion of the inward curving spacer respectively, and a central point defined at the central portion of the inward curving spacer.

9. The semiconductor structure of claim 8, wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two top points of the two inward curving spacers.

10. The semiconductor structure of claim 8, wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two bottom points of the two inward curving spacers.

11. The semiconductor structure of claim 7, wherein the first gate structure is an N-type metal oxide semiconductor field effect transistor (NMOSFET).

12. The semiconductor structure of claim 7, further comprising a second gate structure disposed in the ILD, wherein the second gate structure comprises a second gate electrode and two outward curving spacers disposed on two sides of the gate electrode.

13. The semiconductor structure of claim 12, wherein the second gate structure is a P-type metal oxide semiconductor field effect transistor (PMOSFET).

14. A semiconductor structure, comprising:

a substrate, having an interlayer dielectric (ILD) disposed thereon;

a first gate structure, disposed in the ILD, wherein the first gate structure comprises a gate electrode and two inward curving spacers disposed on two sides of the gate electrode, and the gate electrode has four inward curving sidewalls; and

an epitaxial layer disposed on the substrate and adjacent to the inward curving spacer, and the epitaxial layer has a flattened hexagonal structure.

15. The semiconductor structure of claim 14, wherein each inward curving spacer comprises a top point and a bottom point defined at the topmost portion and at the bottommost portion of the inward curving spacer respectively, and a central point defined at the central portion of the inward curving spacer.

16. The semiconductor structure of claim 15, wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two top points of the two inward curving spacers.

17. The semiconductor structure of claim 15, wherein the shortest distance between two central points of the two inward curving spacers is shorter than the shortest distance between two bottom points of the two inward curving spacers.

18. The semiconductor structure of claim 14, wherein the first gate structure is an N-type metal oxide semiconductor field effect transistor (NMOSFET).

19. The semiconductor structure of claim 14, further comprising a second gate structure disposed in the ILD, wherein the second gate structure comprises a second gate electrode and two outward curving spacers disposed on two sides of the gate electrode.

20. The semiconductor structure of claim 19, wherein the second gate structure is a P-type metal oxide semiconductor field effect transistor (PMOSFET).