Superjunction power semiconductor device and method for forming

• US 10,153,357 B1
• Filed: 08/28/2017
• Issued: 12/11/2018
• Est. Priority Date: 08/28/2017
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Qin, Ganming, Khemka, Vishnu, Saxena, Tanuj, Zitouni, Moaniss, Gupta, Raghuveer Vankayala, Gibson, Mark Edward
• Primary Examiner(s): Ahmed, Selim
• Assistant Examiner(s): Clinton, Evan
• Application Number:
  US15/687,881
• Time in Patent Office: 470 Days
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a super junction power MOSFET includes forming a first trench in a substrate, forming a first oxide layer over the substrate and in the bottom and along sidewalls of the trench, depositing electrically conductive material in the trench, masking a first portion of the electrically conductive material, forming a recessed portion of the electrically conductive material, forming an oxide portion over and in contact with the recessed portion of the electrically conductive material, removing a part of the oxide portion by masking, removing the first oxide layer on the sidewalls while another part of the oxide portion remains in contact with the recessed portion of the electrically conductive material, forming a gate dielectric along exposed sidewalls of the trench, and depositing additional electrically conductive material over the other part of the oxide portion in the trench.

Claims

1. A method for manufacturing a super junction power MOSFET comprising:

forming a first trench in a semiconductor substrate;

forming a first oxide layer over the semiconductor substrate and in the first trench, wherein the first oxide layer is along a bottom and sidewalls of the first trench;

depositing electrically conductive material in the first trench to form a first shield electrode;

masking a first portion of the electrically conductive material in the first trench;

forming a recessed portion of the electrically conductive material (44) by removing a part of a second portion of the electrically conductive material while the first portion of the electrically conductive material is masked;

forming an oxide portion over and in contact with the recessed portion of the electrically conductive material;

removing a part of the oxide portion in the first trench;

removing the first oxide layer on the sidewalls of the trench while another part of the oxide portion remains in contact with the recessed portion of the electrically conductive material;

forming a gate dielectric along exposed sidewalls of the first trench; and

depositing additional electrically conductive material over the other part of the oxide portion in the first trench,

wherein the removing the part of the oxide portion in the first trench includes masking the substrate with a second mask that includes an opening over the first trench that covers the gate dielectric and exposes a central portion of the oxide portion.

2. The method of claim 1 further comprising:

forming a second trench in the semiconductor substrate;

forming the first oxide layer along a bottom and sidewalls of the second trench;

depositing the electrically conductive material in the second trench to form a second shield electrode; and

masking the second shield electrode while forming the recessed portion of the electrically conductive material in the first trench.

3. The method of claim 1 further comprising:

forming a hard mask layer over the semiconductor substrate before forming the first trench, wherein forming the first trench removes a portion of the hard mask layer over the first trench.

4. The method of claim 3 wherein:

the first oxide layer is blanket deposited over the hard mask and along the bottom and sidewalls of the first trench.

5. The method of claim 2 wherein:

the electrically conductive material in the first trench is polysilicon.

6. The method of claim 3 further comprising:

performing chemical-mechanical polishing to remove material extending above a nitride layer in the hard mask before the masking the first portion of the electrically conductive material in the first trench.

7. The method of claim 1 wherein:

the removing a part of a second portion of the electrically conductive material includes removing 30 to 50 percent of the electrically conductive material in the second portion.

8. The method of claim 1 further comprising:

performing chemical-mechanical polishing to remove material extending above the nitride layer after the forming an oxide portion over and in contact with the recessed portion of the electrically conductive material before removing the part of the oxide portion in the first trench.

9. The method of claim 1 wherein:

the removing the first oxide layer on the sidewalls of the trench includes isotropically etching the first oxide layer using the second mask.

10. A method of making a semiconductor device comprising:

forming a first mask over a semiconductor substrate, wherein

the substrate includes a major surface covered with a nitride material, a first trench and a second trench in the major surface, the first and second trenches include a dielectric material along respective sidewalls and are filled with a first polysilicon material, and

the first mask is configured to completely cover the first trench and only a portion of the second trench;

removing a portion of the first polysilicon material from an unmasked portion of the second trench;

removing the first mask;

depositing a second dielectric material that fills the first and second trenches;

forming a second mask over the nitride material on the substrate with an opening over the second trench, wherein the second mask overhangs a portion of the second dielectric material in the second trench;

removing an unmasked portion of the second dielectric material in the second trench so that some of the second dielectric material remains over the first polysilicon material in the second trench and along the sidewalls of the second trench to form first and second shield electrodes;

removing the second dielectric material along the sidewalls of the second trench while the some of the second dielectric material remains over the first polysilicon material in the second trench;

removing the second mask;

forming a third dielectric material along the sidewalls of the second trench; and

filling the second trench with a second polysilicon material to form a first gate electrode.

11. The method of claim 10 further comprising:

the forming the second mask includes the second mask being shaped to mask more of the second dielectric material along a length of the second trench than of a width of the second trench.

12. The method of claim 11 wherein a length of 0.5 to 5 micrometers of the second dielectric material along the length of the second trench remains up to a top of the second trench after the second dielectric material along the sidewalls of the second trench is removed to form an inter-poly dielectric.

13. The method of claim 10 wherein the first mask is shaped so that a remaining portion of the first polysilicon material in the second trench extends up to a top of the second trench after the portion of the first polysilicon material from the unmasked portion of the second trench is removed.

14. The method of claim 10 wherein a thickness of 0.2 to 0.25 micrometers of the second dielectric material remains over the first polysilicon material in the second trench after the second dielectric material along the sidewalls of the second trench is removed.

15. The method of claim 10 further comprising:

removing the nitride material after the third dielectric is formed and the second trench is filled with the second polysilicon material.

16. The method of claim 15 further comprising:

forming a doped implant region in a top portion of the semiconductor substrate between the first and second trenches;

forming a fourth dielectric material over the substrate; and

forming a contact in the fourth dielectric over and in contact with the first gate electrode.

17. The method of claim 10 further comprising:

forming a third shield electrode in a third trench in the major surface of the semiconductor substrate simultaneously with the first and second trenches, wherein the third shield electrode is formed on an opposite side of the second shield electrode from the first shield electrode, wherein

the third trench includes the dielectric material along sidewalls of the third trench and is filled with the first polysilicon material, and

the first mask is configured to completely cover only a portion of the third trench;

removing a portion of the first polysilicon material from an unmasked portion of the third trench;

depositing a second dielectric material that fills the third trench;

the second mask overhangs a portion of the second dielectric material in the third trench;

removing an unmasked portion of the second dielectric material in the third trench so that some of the second dielectric material remains over the first polysilicon material in the third trench and along the sidewalls of the third trench to form a third shield electrode.

18. The method of claim 17 further comprising:

removing the second dielectric material along the sidewalls of the third trench while some of the second dielectric material remains over the first polysilicon material in the third trench;

forming the third dielectric material along the sidewalls of the third trench; and

filling the third trench with a second polysilicon material to form a second gate electrode.

19. The method of claim 18 further comprising:

forming a doped implant region in a top portion of the semiconductor substrate between the second and third trenches;

forming a second contact in the fourth dielectric over and in contact with the second gate electrode.