Semiconductor device and a method of making a semiconductor device

• US 10,153,365 B2
• Filed: 08/10/2016
• Issued: 12/11/2018
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Inventors: Peake, Steven Thomas, Rutter, Philip, Rogers, Chris
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US15/233,834
• Publication Number:
  US 20170077291A1
• Time in Patent Office: 853 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first conductivity type;

a layer of doped silicon located on the substrate;

a trench extending into the layer of silicon;

a gate electrode and gate dielectric located in the trench;

a drain region;

a body region having a second conductivity type located adjacent the trench and above the drain region; and

a source region having the first conductivity type located adjacent the trench and above the body region,

wherein the layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within the region beneath the body region by compensation,

wherein the net doping concentration of the layer of doped silicon as a function of depth has a minimum for the entire semiconductor device in the region located immediately beneath the body region, and

a cap layer located at a top of the layer of doped silicon and beneath the body region and the cap layer is lower doped than the layer of doped silicon beneath the cap layer.

2. The device of claim 1, wherein the net doping concentration of the layer of silicon as a function of depth in the region located beneath the body region increases with increasing depth beneath said minimum.

3. The device of claim 1, wherein the gate electrode extends deeper beneath a surface of the layer of doped silicon than the body region.

4. The device of claim 1, further comprising a reduced surface field electrode in the trench, wherein the reduced surface field electrode is operatively connected to the source region.

5. The device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

6. The device of claim 5, wherein the acceptor ions comprise Boron.

7. A power amplifier comprising a semiconductor device according to claim 1.

8. A switched mode power supply comprising a semiconductor device according to claim 1.

9. The device of claim 1, wherein the cap layer is a part of the layer of doped silicon.