Germanium-based barrier modulated cell

• US 10,153,430 B1
• Filed: 06/13/2017
• Issued: 12/11/2018
• Est. Priority Date: 06/13/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Kamalanathan, Deepak, Saenz, Juan
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US15/621,305
• Publication Number:
  US 20180358550A1
• Time in Patent Office: 546 Days
• Field of Search: 257 2, 257 5
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Systems and methods for providing a Barrier Modulated Cell (BMC) structure with reduced shifting in stored memory cell resistance levels over time are described. The BMC structure may comprise a reversible resistance-switching memory element within a memory array comprising a first conductive metal oxide (e.g., titanium oxide) in series with an alternating stack of one or more layers of an amorphous low bandgap material (e.g., germanium) with one or more layers of a second conductive metal oxide (e.g., aluminum oxide). The BMC structure may include a barrier layer comprising a first conductive metal oxide, such as titanium oxide or strontium titanate, in series with a germanium stack that includes a layer of amorphous germanium or amorphous silicon germanium paired with a second conductive metal oxide. The second conductive metal oxide (e.g., aluminum oxide) may be different from the first conductive metal oxide (e.g., titanium oxide).

Claims

1. A memory structure, comprising:

a bit line;

a word line; and

a memory cell arranged between the word line and the bit line, the memory cell includes a first conductive metal oxide in series with an alternating stack of one or more layers of germanium with one or more layers of a second conductive metal oxide different from the first conductive metal oxide, the first conductive metal oxide comprises titanium oxide and the second conductive metal oxide comprises aluminum oxide, a second metal of the second conductive metal oxide has a greater affinity for oxygen compared with a first metal of the first conductive metal oxide.

2. The memory structure of claim 1, wherein:

the alternating stack of the one or more layers of germanium with the one or more layers of the second conductive metal oxide comprises a first layer of germanium adjacent to a first layer of the second conductive metal oxide.

3. The memory structure of claim 2, wherein:

the word line directly connects to the second conductive metal oxide; and

the bit line connects to the first conductive metal oxide.

4. The memory structure of claim 2, wherein:

the alternating stack of the one or more layers of germanium with the one or more layers of the second conductive metal oxide comprises the first layer of germanium adjacent to the first layer of the second conductive metal oxide and a second layer of germanium adjacent to the first layer of the second conductive metal oxide.

5. The memory structure of claim 4, wherein:

the word line directly connects to the second layer of germanium; and

the bit line connects to the first conductive metal oxide.

6. The memory structure of claim 2, wherein:

a thickness of the first layer of germanium is greater than a thickness of the first layer of the second conductive metal oxide.

7. The memory structure of claim 2, wherein:

the alternating stack of the one or more layers of germanium with the one or more layers of the second conductive metal oxide comprises the first layer of germanium adjacent to the first layer of the second conductive metal oxide, a second layer of germanium adjacent to the first layer of the second conductive metal oxide, and a second layer of the second conductive metal oxide adjacent to the second layer of germanium.

8. The memory structure of claim 1, further comprising:

a second memory cell arranged between a second word line and the bit line, the second word line is arranged above the word line, the second memory cell includes a third conductive metal oxide in series with an alternating stack of one or more layers of germanium with one or more layers of a fourth conductive metal oxide different from the third conductive metal oxide.

9. The memory structure of claim 1, wherein:

the memory cell comprises a multi-level memory cell; and

the bit line comprises a vertical bit line arranged orthogonal to a surface of a substrate.

10. An apparatus, comprising:

a memory array including a word line and a bit line, the memory array includes a memory cell arranged between the word line and the bit line, the memory cell comprises a first conductive metal oxide of a first metal adjacent to a layer of a germanium-metal alloy of a second metal adjacent to a first layer of the second metal, the second metal is different from the first metal, the first metal comprises titanium and the second metal comprises aluminum, the second metal has a greater affinity for oxygen compared with the first metal; and

one or more control circuits configured to bias the word line and the bit line during a memory operation.

11. The apparatus of claim 10, wherein:

the memory operation comprises a read operation;

the first conductive metal oxide comprises titanium dioxide; and

the layer of the germanium-metal alloy of the second metal is arranged between the first conductive metal oxide of the first metal and the first layer of the second metal.

12. The apparatus of claim 10, wherein:

the memory cell comprises a multi-level memory cell; and

the bit line comprises a vertical bit line arranged orthogonal to a surface of a substrate.