Apparatus and method for operating a power amplifier array with enhanced efficiency at back-off power levels

• US 10,153,731 B2
• Filed: 10/23/2017
• Issued: 12/11/2018
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: RF Pixels, Inc. (Skyworks Solutions Incorporated)
• Inventors: Thyagarajan, Siva V., Niknejad, Ali M., Venugopalan, Sriramkumar
• Primary Examiner(s): Le, Thanh
• Application Number:
  US15/791,312
• Publication Number:
  US 20180115282A1
• Time in Patent Office: 414 Days
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/2175 using analogue-digital or digital-analogue conversion H03F3/2173 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0458 Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages matching circuits in general H03H
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control
• CPC Class Codes: H04B 2001/045 with means for improving efficiency

Abstract

An apparatus, comprising has an array of power amplifiers. A power detector collects a power signal applied to the array of power amplifiers. Digital logic is connected to the array of power amplifiers and the power detector. The digital logic is configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers. Each array pattern in the set of array patterns includes at least one operative power amplifier.

Claims

1. An apparatus, comprising:

an array of power amplifiers;

a power detector to collect a power signal applied to the array of power amplifiers; and

digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier;

wherein the array pattern is different than a previous array pattern, wherein the previous array patterns has a first set of power amplifiers operating at peak efficiency and a previous power amplifier with output power below a cut-off point, and the array pattern has a new set of power amplifiers operating at peak efficiency and a new power amplifier operating in a continuous manner above the cut-off point.

2. The apparatus of claim 1 wherein the array pattern has a majority of power amplifiers operating at peak efficiency level.

3. The apparatus of claim 2 wherein the array pattern has a minority of power amplifiers whose output power changes with the power signal.

4. The apparatus of claim 1 wherein the digital logic is configured to select the array pattern based upon a power amplifier configuration that adds hysteresis to the array of power amplifiers and thereby prevents excessive switching of power amplifiers.

5. The apparatus of claim 1 wherein the digital logic is configured to select the array pattern and generate the control signal during a dead zone period of no signal transmission.

6. The apparatus of claim 1 wherein the array of power amplifiers is one of a plurality of arrays of power amplifiers in a multiple-input and multiple-output (MIMO) system and wherein the digital logic is configured to estimate distances from users and determine for each user whether a full array of the MIMO system or a sub-array of the MIMO system is utilized.

7. An apparatus, comprising:

an array power amplifier;

a power detector to collect a power signal applied to the array of power amplifiers;

digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier; and

an asymmetric power divider connected to the array of power amplifiers and the digital logic, the asymmetric power divider splitting the power signal into N parts with N−

1 parts being substantially equal and constant to achieve peak power amplifier efficiency and a single part with power at varies based on the power signal.

8. The apparatus claim 7 wherein each power amplifier in the array of power has linear operation for a peak to average power ratio.

9. The apparatus of claim 7 wherein the digital logic is configured to implement a dynamic power back-off in which power amplifiers of the array of power amplifiers are turned on and off based on the power signal.

10. The apparatus of claim 7 wherein the digital logic is configured to select an array pattern the produces minimal side lobes.

11. The apparatus of claim 7 wherein each power amplifier in the array of power amplifiers is a segment of a transmitter chain that includes an analog-to-digital converter, a filter, a mixer and an antenna.

12. The apparatus of claim 7 wherein each power amplifier in the array of power amplifiers is a segment of a transmitter chain that includes a variable gain amplifier and a phase shifter.

13. An apparatus, comprising:

an array of power amplifiers;

a power detector to collect a power signal applied to the array of power amplifiers; and

digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier;

wherein the array of power amplifiers is a two dimensional array of power amplifiers and the digital logic selects an array pattern that includes at least one of a new row of power amplifiers turned on, a new column of amplifiers turned on and a mixed power amplifier collection turned on.

14. The apparatus of claim 13 wherein the digital logic is configured to implement a static power back-off in which the average power of the array of power amplifiers is changed based on a geographic relationship between a client device and the array of power amplifiers.

15. The apparatus of claim 14 wherein the array of power amplifiers is one of a plurality of arrays of power amplifiers in a multiple-input and multiple-output (MIMO) system with a sub-array of power amplifiers that implements the static power back-off for a user.

16. The apparatus of claim 14 wherein the array of power amplifiers is one of a plurality of arrays of power amplifiers in a multiple-input and multiple-output (MIMO) system that implements the static power back-off based upon a combination of user streams that are applied to the MIMO system with appropriate phase shifts, such that the static power back-off for an individual user depends on the relative power levels of the different user streams in the combination.