Apparatus and method for operating a power amplifier array with enhanced efficiency at back-off power levels
First Claim
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1. An apparatus, comprising:
- an array of power amplifiers;
a power detector to collect a power signal applied to the array of power amplifiers; and
digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier;
wherein the array pattern is different than a previous array pattern, wherein the previous array patterns has a first set of power amplifiers operating at peak efficiency and a previous power amplifier with output power below a cut-off point, and the array pattern has a new set of power amplifiers operating at peak efficiency and a new power amplifier operating in a continuous manner above the cut-off point.
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Abstract
An apparatus, comprising has an array of power amplifiers. A power detector collects a power signal applied to the array of power amplifiers. Digital logic is connected to the array of power amplifiers and the power detector. The digital logic is configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers. Each array pattern in the set of array patterns includes at least one operative power amplifier.
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Citations
16 Claims
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1. An apparatus, comprising:
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an array of power amplifiers; a power detector to collect a power signal applied to the array of power amplifiers; and digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier; wherein the array pattern is different than a previous array pattern, wherein the previous array patterns has a first set of power amplifiers operating at peak efficiency and a previous power amplifier with output power below a cut-off point, and the array pattern has a new set of power amplifiers operating at peak efficiency and a new power amplifier operating in a continuous manner above the cut-off point. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus, comprising:
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an array power amplifier; a power detector to collect a power signal applied to the array of power amplifiers; digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier; and an asymmetric power divider connected to the array of power amplifiers and the digital logic, the asymmetric power divider splitting the power signal into N parts with N−
1 parts being substantially equal and constant to achieve peak power amplifier efficiency and a single part with power at varies based on the power signal. - View Dependent Claims (8, 9, 10, 11, 12)
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13. An apparatus, comprising:
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an array of power amplifiers; a power detector to collect a power signal applied to the array of power amplifiers; and digital logic connected to the array of power amplifiers and the power detector, the digital logic configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers, wherein each array pattern in the set of array patterns includes at least one operative power amplifier; wherein the array of power amplifiers is a two dimensional array of power amplifiers and the digital logic selects an array pattern that includes at least one of a new row of power amplifiers turned on, a new column of amplifiers turned on and a mixed power amplifier collection turned on. - View Dependent Claims (14, 15, 16)
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Specification