Programmable input/output circuit

• US 10,153,770 B2
• Filed: 12/05/2016
• Issued: 12/11/2018
• Est. Priority Date: 05/05/2009
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Timothy John, Wright, David G., Verge, Gregory John, Byrkett, Bruce E.
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US15/369,674
• Publication Number:
  US 20170194963A1
• Time in Patent Office: 736 Days
• Field of Search: 326 82- 83, 326 86- 87, 327108-109
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/01759 with a bidirectional operation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Claims

1. A system, comprising:

a processing system disposed on a first integrated circuit, the processing system comprising a processor, a storage device, and a system input/output (I/O); and

an intermediate circuit to couple to the system I/O and disposed outside of the processing system on a second integrated circuit, the intermediate circuit including, a terminal configured to receive a supply voltage, and a circuit I/O pin, wherein the circuit I/O pin is configured to receive a first analog signal from a first device and a second analog signal from second device, the first and second devices each disposed outside of the second integrated circuit of the intermediate circuit wherein the intermediate circuit is configured determine a logic level of the first analog signal using a first reference voltage and determine a logic level of the second analog signal using a second reference voltage.

2. The system of claim 1, wherein the device comprises a peripheral device configured to provide an input signal to the circuit I/O pin and receive an output signal from the circuit I/O pin.

3. The system of claim 1, wherein the circuit I/O pin is configured to receive a first signal having a first voltage level and second signal having a second voltage level.

4. The system of claim 1, wherein each of the first device and the second device is a peripheral device including circuitry configured to perform a function responsive to a command from the processing system.

5. The system of claim 1, wherein the intermediate circuit comprises one or more components that are powered by the supply voltage.

6. The system of claim 1, wherein the intermediate circuit is configured to alternately switch between using the first reference voltage and using the second reference voltage during operation.