128 gigabit fibre channel physical architecture

• US 10,153,989 B2
• Filed: 08/31/2016
• Issued: 12/11/2018
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, LLC (Broadcom, Inc.)
• Inventors: Mehta, Anil, Kipp, Scott
• Primary Examiner(s): Kumar, Shailendra
• Application Number:
  US15/253,666
• Publication Number:
  US 20160373379A1
• Time in Patent Office: 832 Days
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04L 12/4013 Management of data rate on the bus systems modifying transmission characteristics according to link quality H04L1/0001
• CPC Class Codes: H04L 41/0681 Configuration of triggering conditions
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 69/321 Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers

Abstract

The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.

Claims

1. A physical layer network interface link apparatus comprising:

a media access control (MAC) interface for connection to a MAC layer providing or receiving a stream of 64 bit blocks;

a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes;

a transmit path connected to and between said MAC interface and to said PMA interface; and

a receive path connected to and between said MAC interface and to said PMA interface,

wherein said transmit path includes;

an encode module connected to said MAC interface;

a scramble module connected to said encode module;

a block distribution module connected to said scramble module;

a transmit transcode module to transcode from 64b/66b blocks to 256b/257b blocks coupled to said block distribution module;

an alignment marker insertion module connected to said transmit transcode module;

a Reed-Solomon (RS) forward error correction (FEC) encode module connected to said alignment marker insertion module; and

a symbol distribution module connected to said RS FEC encode module and said PMA interface, and

wherein said receive path further includes;

an alignment lock and deskew module connected to said PMA interface;

a lane reorder module connected to said alignment lock and deskew module;

an RS FEC decoder module connected to said lane reorder module;

an alignment marker removal module connected to said RS FEC decoder module;

a receive transcode module to transcode from 256b/257b blocks to 64b/66b blocks connected to said alignment marker removal module;

a descramble module coupled to said receive transcode module; and

a decode module connected to said descramble module and said MAC interface, and

wherein said alignment markers are in the form of an alignment marker pair, said alignment marker pair including a first alignment marker for lane zero and a second alignment marker for the appropriate lane on which said alignment marker pair is provided.

2. The apparatus of claim 1, wherein said transmit path and said receive path operate using only four lanes.

3. The apparatus of claim 1, wherein said alignment markers do not include bit interleaved parity (BIP) fields but include fixed DC balanced values instead.

4. The apparatus of claim 1, wherein the network interface link is a 128 Gbps Fibre Channel network link.

5. A physical layer network interface link apparatus comprising:

a media access control (MAC) layer having an interface providing or receiving a stream of 64 bit blocks;

a transmit path; and

a receive path,

wherein said transmit path includes;

an encode module connected to said MAC interface;

a scramble module connected to said encode module;

a block distribution module connected to said scramble module;

a transmit transcode module to transcode from 64b/66b blocks to 256b/257b blocks coupled to said block distribution module;

an alignment marker insertion module connected to said transmit transcode module;

a Reed-Solomon (RS) forward error correction (FEC) encode module connected to said alignment marker insertion module; and

a symbol distribution module connected to said RS FEC encode module and for connection to a physical media attachment (PMA) interface, and

wherein said receive path further includes;

an alignment lock and deskew module for connection to the PMA interface;

a lane reorder module connected to said alignment lock and deskew module;

an RS FEC decoder module connected to said lane reorder module;

an alignment marker removal module connected to said RS FEC decoder module;

a receive transcode module to transcode from 256b/257b blocks to 64b/66b blocks connected to said alignment marker removal module;

a descramble module coupled to said receive transcode module;

a decode module connected to said descramble module and said MAC interface, and

wherein said alignment markers are in the form of an alignment marker pair, said alignment marker pair including a first alignment marker for lane zero and a second alignment marker for the appropriate lane on which said alignment marker pair is provided.

6. The apparatus of claim 5, wherein said transmit path and said receive path operate using only four lanes.

7. The apparatus of claim 5, wherein said alignment markers do not include bit interleaved parity (BIP) fields but include fixed DC balanced values instead.

8. The apparatus of claim 5, wherein the network interface link is a 128 Gbps Fibre Channel network link.

9. A network switch comprising:

a control processor;

memory coupled to said control processor; and

a switching system coupled to said control processor, said switching system including;

a frame data storage system;

a header processing system coupled to said frame data storage system; and

a plurality of ports coupled to said frame data storage system, each of said plurality of ports including;

a frame data storage system interface coupled to said frame data storage system; and

a physical layer network interface link apparatus including;

a transmit path for connection to and between a media access control (MAC) interface and to a physical media attachment (PMA) interface; and

a receive path for connection to and between the MAC interface and to the PMA interface,

wherein said transmit path includes;

 

an encode module for connection to the MAC interface;

 

a scramble module connected to said encode module;

 

a block distribution module connected to said scramble module;

 

a transmit transcode module to transcode from 64b/66b blocks to 256b/257b blocks coupled to said block distribution module;

 

an alignment marker insertion module connected to said transmit transcode module;

 

a Reed-Solomon (RS) forward error correction (FEC) encode module connected to said alignment marker insertion module; and

 

a symbol distribution module connected to said RS FEC encode module and for connection to the PMA interface, and

wherein said receive path further includes;

 

an alignment lock and deskew module for connection to the PMA interface;

 

a lane reorder module connected to said alignment lock and deskew module;

 

an RS FEC decoder module connected to said lane reorder module;

 

an alignment marker removal module connected to said RS FEC decoder module;

 

a receive transcode module to transcode from 256b/257b blocks to 64b/66b blocks connected to said alignment marker removal module;

 

a descramble module coupled to said receive transcode module; and

 

a decode module connected to said descramble module and for connection to the MAC interface, and

wherein said alignment markers are in the form of an alignment marker pair, said alignment marker pair including a first alignment marker for lane zero and a second alignment marker for the appropriate lane on which said alignment marker pair is provided.

10. The network switch of claim 9, wherein said transmit path and said receive path operate using only four lanes.

11. The network switch of claim 9, wherein said alignment markers do not include bit interleaved parity (BIP) fields but include fixed DC balanced values instead.

12. The network switch of claim 9, wherein the external network interface link is a 128 Gbps Fibre Channel network link.