Power supply glitch detector

• US 10,156,595 B2
• Filed: 12/04/2017
• Issued: 12/18/2018
• Est. Priority Date: 12/09/2016
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Microsemi SoC Corp.
• Inventors: Nirwan, Bhawana Singh, Lal, Abhishek
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US15/831,287
• Publication Number:
  US 20180164351A1
• Time in Patent Office: 379 Days
• Field of Search: None
• CPC Class Codes: G01R 19/165 Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
• CPC Class Codes: G01R 19/16547 voltage or current in AC supplies switching for protection H02H; circuits for emergency power supply H02J9/00
• CPC Class Codes: G01R 19/25 using digital measurement techniques
• CPC Class Codes: G01R 19/2503 for measuring voltage only, e.g. digital volt meters (DVM's) G01R19/2506 - G01R19/257 take precedence
• CPC Class Codes: G01R 29/02 Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
• CPC Class Codes: G01R 29/023 Measuring pulse width
• CPC Class Codes: G01R 29/027 Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
• CPC Class Codes: G01R 29/0273 the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
• CPC Class Codes: G01R 29/0276 the pulse characteristic being rise time measuring rate of change G01R19/12
• CPC Class Codes: G01R 31/317 Testing of digital circuits
• CPC Class Codes: G01R 31/40 Testing power supplies testing photovoltaic devices H02S50/10
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H03K 5/04 by increasing duration; by decreasing duration
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V_glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V_trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V_bias, wherein V_bias is chosen such that either both conditions (V_bias<V_trip) and (V_bias+V_glitch>V_trip) or both conditions (V_bias>V_trip) and (V_bias−V_glitch<V_trip) are always true.

Claims

1. A power supply glitch detector comprising:

a sensing node AC coupled to a power supply node on which positive voltage glitches having a magnitude of at least V_glitch are to be detected;

a sensing inverter having an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V_trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state; and

a user-settable voltage biasing circuit coupled to the sensing node to maintain the input of the sensing inverter at a settable bias voltage V_bias, wherein V_bias is chosen such that both conditions (V_bias<

V_trip) and (V_bias+V_glitch>

V_trip) are always true.

2. The power supply glitch detector of claim 1 wherein the sensing node is AC coupled by a capacitor voltage divider to the power supply node on which positive voltage glitches having a magnitude of at least V_glitch are to be detected.

3. The power supply glitch detector of claim 1 further comprising a glitch width filter coupled to the output of the sensing inverter.

4. The power supply glitch detector of claim 3 wherein the glitch width filter is a variable pulse width filter.

5. The power supply glitch detector of claim 1 further comprising a pulse stretching circuit coupled to the output of the sensing inverter.

6. The power supply glitch detector of claim 1 wherein the user-settable voltage biasing circuit comprises:

a series string of resistors;

an inverter having a trip voltage V_trip equal to the trip voltage of the sensing inverter, the inverter having an input and an output connected together to a first end of the series string of resistors;

an n-channel transistor having a drain coupled to a second end of the series string of resistors, a source coupled to ground, and a gate coupled to a voltage potential selected to cause a predetermined current to flow through the series string of resistors;

a first select transistor coupled between the drain of the n-channel transistor and the sensing node, the first select transistor having a gate coupled to a first control signal; and

a second select transistor coupled between a common connection of a first adjacent pair of resistors in the series string of resistors and the sensing node, the second select transistor having a gate coupled to a second control signal.

7. The power supply glitch detector of claim 6 wherein the user-settable voltage biasing circuit further comprises:

a third select transistor coupled between a common connection of a second adjacent pair of resistors in the series string of resistors and the sensing node, the third select transistor having a gate coupled to a third control signal.

8. A power supply glitch detector comprising:

a sensing node AC coupled to a power supply node on which negative voltage glitches having a magnitude of at least V_glitch are to be detected;

a sensing inverter having an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V_trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state;

a user-settable voltage biasing circuit coupled to the sensing node to maintain the input of the sensing inverter at a settable bias voltage V_bias, wherein V_bias is chosen such that both conditions (V_bias>

V_trip) and (V_bias−

V_glitch<

V_trip) are always true.

9. The power supply glitch detector of claim 8 wherein the sensing node is AC coupled by a capacitor voltage divider to the power supply node on which negative voltage glitches having a magnitude of at least V_glitch are to be detected.

10. The power supply glitch detector of claim 8 further comprising a glitch width filter coupled to the output of the sensing inverter.

11. The power supply glitch detector of claim 10 wherein the glitch width filter is a variable pulse width filter.

12. The power supply glitch detector of claim 8 further comprising a pulse stretching circuit coupled to the output of the sensing inverter.

13. The power supply glitch detector of claim 8 wherein the user-settable voltage biasing circuit comprises:

a series string of resistors;

a current mirror supplying a current i_bias connected to a first end of the series string of resistors;

an inverter having a trip voltage V_trip equal to the trip voltage of the sensing inverter, the inverter having an input and an output connected together to a second end of the series string of resistors;

a first select transistor coupled between the output of the current mirror and the sensing node, the first select transistor having a gate coupled to a first control signal; and

a second select transistor coupled between a common connection of a first adjacent pair of resistors in the series string of resistors and the sensing node, the second select transistor having a gate coupled to a second control signal.

14. The power supply glitch detector of claim 13 wherein the user-settable voltage biasing circuit further comprises:

a third select transistor coupled between a common connection of a second adjacent pair of resistors in the series string of resistors and the sensing node, the third select transistor having a gate coupled to a third control signal.

15. A power supply glitch detector comprising:

a first sensing node AC coupled to a power supply node on which positive voltage glitches having a magnitude of at least V_glitch+ are to be detected;

a first sensing inverter having an input and an output, the input coupled to the first sensing node, the first sensing inverter having a trip voltage V_trip+ below which the output of the first sensing inverter is at a voltage representing a logic high state and above which the output of the first sensing inverter is at a voltage representing a logic low state;

a first user-settable voltage biasing circuit coupled to the first sensing node to maintain the input of the first sensing inverter at a settable bias voltage V_bias+, wherein V_bias+ is chosen such that both conditions (V_bias+<

V_trip+) and (V_bias++V_glitch+>

V_trip+) are always true;

a second sensing node AC coupled to a power supply node on which negative voltage glitches having a magnitude of at least V_glitch−

are to be detected;

a second sensing inverter having an input and an output, the input coupled to the second sensing node, the second sensing inverter having a trip voltage V_trip−

below which the output of the second sensing inverter is at a voltage representing a logic high state and above which the output of the second sensing inverter is at a voltage representing a logic low state;

a second user-settable voltage biasing circuit coupled to the second sensing node to maintain the input of the second sensing inverter at a settable bias voltage V_bias−

, wherein V_bias−

is chosen such that both conditions (V<sub>bia−

s</sub>>

V_trip−

) and (V_bias−

−

V_glitch−

<

V_trip−

) are always true.

16. The power supply glitch detector of claim 15 wherein:

the first sensing node is AC coupled by a first capacitor voltage divider coupled to the power supply node on which positive voltage glitches having a magnitude of at least V_glitch+ are to be detected; and

the second sensing node is AC coupled by a second capacitor voltage divider coupled to the power supply node on which negative voltage glitches having a magnitude of at least V_glitch−

are to be detected.

17. The power supply glitch detector of claim 16 further comprising:

a first glitch width filter coupled to the output of the first sensing inverter; and

a second glitch width filter coupled to the output of the second sensing inverter.

18. The power supply glitch detector of claim 17 wherein the first and second glitch width filters are variable pulse width filters.

19. The power supply glitch detector of claim 16 further comprising:

a first pulse stretching circuit coupled to the output of the first sensing inverter; and

a second pulse stretching circuit coupled to the output of the second sensing inverter.