Flash memory apparatus and storage management method for flash memory

• US 10,157,098 B2
• Filed: 06/04/2018
• Issued: 12/18/2018
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: Yang, Tsung-Chieh, Hsu, Hong-Jung, Du, Jian-Dong
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/997,674
• Publication Number:
  US 20180285195A1
• Time in Patent Office: 197 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Claims

1. A flash memory apparatus, comprising:

a flash memory module comprising a plurality of storage blocks, a cell of each storage block can be used for storing data of 1 bit or data of at least 2 bits; and

a flash memory controller, configured for classifying data to be programmed into a plurality of groups of data, respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks;

wherein the flash memory controller is further arranged for reading out the groups of data from the first blocks, executing error correction and de-randomize operation upon read out data to generate de-randomized data, executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data, performing error code encoding upon the randomized data to generate a second corresponding parity check code, storing the randomized data and the second corresponding parity check code into the flash memory module as a second block;

a cell of a first block is used for storing data of a first bit number which is different from a second bit number, a cell of the second block being arranged for storing data of the second bit number.

2. The flash memory apparatus of claim 1, wherein the cell of the second block is arranged for storing data of 3 bits, and the second block is a triple-level-cell block, and the flash memory controller is arranged for classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

3. The flash memory apparatus of claim 1, wherein the flash memory controller comprises:

a decoding circuit, configured for executing the error correction upon the read out data;

a de-randomizer, coupled to the decoding circuit, configured for performing the de-randomize operation upon the readout data to generate the de-randomized data;

a randomizer, coupled to the de-randomizer, configured for executing the randomize operation upon the de-randomized data according to the set of seeds to generate the randomized data; and

an encoding circuit, coupled to the randomizer, configured for performing the error code encoding upon the randomized data to generate the second corresponding parity check code.

4. A flash memory storage management method used for a flash memory module having a plurality of storage blocks, a cell of each storage block can be used for storing data of 1 bit or data of at least 2 bits, and the flash memory storage management method comprises:

classifying data to be programmed into a plurality of groups of data;

respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks;

reading out the groups of data from the first blocks;

executing error correction and de-randomize operation upon read out data to generate de-randomized data;

executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data;

performing error code encoding upon the randomized data to generate a second corresponding parity check code; and

storing the randomized data and the second corresponding parity check code into the flash memory module as a second block;

wherein a cell of a first block is used for storing data of a first bit number which is different from a second bit number, a cell of the second block being arranged for storing data of the second bit number.

5. The method of claim 4, wherein the cell of the second block is arranged for storing data of 3 bits, and the second block is a triple-level-cell block, and the step of classifying the data to be programmed into the plurality of groups of data comprises:

classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.

6. A flash memory controller connected to a flash memory module having a plurality of storage blocks, a cell of each storage block can be used for storing data of 1 bit or data of at least 2 bits, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks, and the flash memory controller comprises:

a decoding circuit, configured for executing error correction upon read out data which is read out by the flash memory controller from the first blocks;

a de-randomizer, coupled to the decoding circuit, configured for performing a de-randomize operation upon the read out data to generate de-randomized data;

a randomizer, coupled to the de-randomizer, configured for executing a randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; and

an encoding circuit, coupled to the randomizer, configured for performing the error code encoding upon the randomized data to generate a second corresponding parity check code;

wherein the flash memory controller is arranged for storing the randomized data and the second corresponding parity check code into the flash memory module as a second block;

a cell of a first block is used for storing data of a first bit number which is different from a second bit number, a cell of the second block being arranged for storing data of the second bit number.

7. The flash memory controller of claim 6, wherein the cell of the second block is arranged for storing data of 3 bits, and the second block is a triple-level-cell block, and the flash memory controller is arranged for classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks.