Decreasing the data handoff interval for a reserved cache line based on an early indication of a systemwide coherence response
First Claim
1. A method of data processing in a multiprocessor data processing system including multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies, the method comprising:
- in response to receipt of a load-and-reserve request from a first processor core, a first cache memory in a first vertical cache hierarchy supporting the first processor core issuing on the system interconnect an interconnect memory access request for a target cache line of the load-and-reserve request;
responsive to the interconnect memory access request and prior to receiving a systemwide coherence response for the interconnect memory access request, the first cache memory receiving from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the interconnect memory access request; and
in response to receiving a store-conditional request from the first processor core and the early indication of the systemwide coherence response, and prior to receiving the systemwide coherence response, the first cache memory initiating servicing of the store-conditional request to update the target cache line in the first cache memory.
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Accused Products
Abstract
A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request. In response to the early indication and prior to receiving the systemwide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.
5 Citations
18 Claims
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1. A method of data processing in a multiprocessor data processing system including multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies, the method comprising:
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in response to receipt of a load-and-reserve request from a first processor core, a first cache memory in a first vertical cache hierarchy supporting the first processor core issuing on the system interconnect an interconnect memory access request for a target cache line of the load-and-reserve request; responsive to the interconnect memory access request and prior to receiving a systemwide coherence response for the interconnect memory access request, the first cache memory receiving from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the interconnect memory access request; and in response to receiving a store-conditional request from the first processor core and the early indication of the systemwide coherence response, and prior to receiving the systemwide coherence response, the first cache memory initiating servicing of the store-conditional request to update the target cache line in the first cache memory. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A processing unit for a multiprocessor data processing system, the processing unit comprising:
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a processor core; interconnect logic configured to couple the processing unit to a system interconnect of the multiprocessor data processing system; a first vertical cache hierarchy supporting the processor core, the first vertical cache hierarchy including a first cache memory that is configured to; in response to receipt of a load-and-reserve request from the processor core, issue on the system interconnect an interconnect memory access request for a target cache line of the load-and-reserve request; responsive to the interconnect memory access request and prior to receiving a systemwide coherence response for the interconnect memory access request, receive from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the interconnect memory access request; and in response to receiving a store-conditional request from the first processor core and the early indication of the systemwide coherence response, and prior to receiving the systemwide coherence response, initiate servicing of the store-conditional request to update the target cache line in the first cache memory. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
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a processing unit for a multiprocessor data processing system, the processing unit comprising; a processor core; interconnect logic configured to couple the processing unit to a system interconnect of the multiprocessor data processing system; a first vertical cache hierarchy supporting the processor core, the first vertical cache hierarchy including a first cache memory that is configured to; in response to receipt of a load-and-reserve request from the processor core, issue on the system interconnect an interconnect memory access request for a target cache line of the load-and-reserve request; responsive to the interconnect memory access request and prior to receiving a systemwide coherence response for the interconnect memory access request, receive from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the interconnect memory access request; and in response to receiving a store-conditional request from the first processor core and the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, initiate servicing of the store-conditional request to update the target cache line in the first cache memory. - View Dependent Claims (15, 16, 17, 18)
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Specification