Systems and methods for reducing standby power in floating body memory devices

• US 10,157,663 B2
• Filed: 03/13/2018
• Issued: 12/18/2018
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Widjaja, Yuniarto
• Primary Examiner(s): Le, Vu
• Application Number:
  US15/920,111
• Publication Number:
  US 20180204611A1
• Time in Patent Office: 280 Days
• Field of Search: 365229, 365226, 365227
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Claims

1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells storing charge representative of data, said method comprising:

counting bits of data before data enters the array, wherein said counting comprises counting at least one of;

a total number of bits at state 1 and a total number of all bits;

a total number of bits at state 0 and the total number of all bits;

or the total number of bits at state 1 and the total number of bits at state 0;

detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0;

setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and

inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

2. The method of claim 1, wherein said floating body memory cells comprise bi-stable SRAM floating body memory cells.

3. The method of claim 1, further comprising

outputting contents of the bits of data from the memory array, wherein said method further comprising inverting the bits of data from the memory array prior to said outputting when the inversion bit has been set.

8. The method of claim 1, further comprising buffering said data with a page buffer prior to said writing.

9. The method of claim 1, comprising checking said inversion bit, prior to reading the data out of said array, wherein when said checking determines that said inversion bit has been set, the data from the memory array is inverted to restore the data to its state prior to the previous inversion.

10. The method of claim 1, further comprising:

identifying at least one row or column of cells of said floating body memory array storing data that is no longer needed; and

setting each of said cells in said at least one row or column to state 0.

11. The method of claim 10, wherein said at least one row or column stores data redundantly.

12. The method of claim 10, wherein said at least one row or column is selected from the group consisting of:

one or more dummy columns, one or more dummy rows, one or more dummy rows and columns, one or more redundant columns, one or more redundant rows, one or more redundant rows and columns, and one or more redundant blocks.

4. A system for reducing standby power, said system comprising:

a memory array comprising a plurality of floating body memory cells configured to store charge representative of data;

a controller configured to control operations of said system;

an inversion bit configured to be set to indicate when an inversion of bit data has been performed;

a counter and detector configured to count bits of the data before the data enters the array, wherein said counting comprises counting at least one of;

a total number of bits at state 1 and a total number of all bits;

a total number of bits at state 0 and the total number of all bits;

or the total number of bits at state 1 and the total number of bits at state 0, and to detect whether the total number of bits at state 1 is greater than the total number of bits at state 0;

wherein when the total number of bits at state 1 is greater than the total number of bits at state 0, said controller sets said inversion bit; and

contents of all the bits of data are inverted before writing the bits of data to the memory array when the inversion bit has been set.

5. The system of claim 4, further comprising a page buffer that receives said data from said counter and detector, buffers said data, and inputs said data to said memory array.

6. The system of claim 4, wherein said inversion bit is checked by said controller, prior to reading the data out of said array, wherein said inversion bit has been set, the data from the memory array is inverted to restore the data to its state prior to the previous inversion.

7. The system of claim 4, configured so that multiple pages, words or bytes of data can share said inversion bit, wherein upon identifying the need to perform a data inversion, any subsets of the data having been previously written to the array are inverted by reading back the subsets having been previously written, inverting and rewriting the subsets back to the array.