SRAM bitline equalization using phase change material

• US 10,157,672 B2
• Filed: 11/13/2017
• Issued: 12/18/2018
• Est. Priority Date: 04/25/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cadigan, David D., Huott, William V., McPadden, Adam J., Saetow, Anuwat
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/810,290
• Publication Number:
  US 20180308545A1
• Time in Patent Office: 400 Days
• Field of Search: 36518905, 36523008, 365148, 365163
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

Claims

1. A method for static random access memory (SRAM) bitline equalization using phase change material (PCM), the method comprising:

detecting a defect in SRAM bitlines;

programming a variable resistance PCM cell to offset the detected defect;

measuring signal development time for the SRAM bitlines; and

adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development time for the SRAM bitlines, wherein an existing transistor of the SRAM is coupled to the variable resistance PCM cell for offsetting the defect, wherein the existing transistor is part of a pre-charge circuit.

2. The method of claim 1, wherein detecting the defect is determined based at least in part on analyzing the signal development time for an array of cells comprising the SRAM bitlines;

determining a distribution of a performance of the signal development time for bitlines of the array of cells;

identifying outlier bitlines in the distribution based at least in part on which bitlines fail prematurely relative to other bitlines in the distribution;

programming the variable resistance PCM cell to a conductive state for outlier bitlines;

measuring the signal development time for the outlier bitlines; and

re-programming the variable resistance PCM cell based at least in part on the measurement of the outlier bitlines.

3. The method of claim 1, wherein if the defect is determined to pull up the bitline of the SRAM, activating the variable resistance PCM cell coupled to the bitline opposite the bitline having the defect.

4. The method of claim 1, wherein if the defect is determined to pull down the bitline of the SRAM, activating the variable resistance PCM cell coupled to the bitline being pulled down.

5. The method of claim 1, further comprising offsetting, by a dedicated transistor, the defect of the variable resistance PCM cell.