Background reference positioning and local reference positioning using threshold voltage shift read

• US 10,157,677 B2
• Filed: 07/20/2017
• Issued: 12/18/2018
• Est. Priority Date: 07/28/2016
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: Ip Gem Group, LLC
• Inventors: Marelli, Alessia, Micheloni, Rino
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/655,639
• Publication Number:
  US 20180033491A1
• Time in Patent Office: 516 Days
• Field of Search: 36518502, 36518509, 36518512, 36518522
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Claims

1. A nonvolatile memory controller comprising:

a status circuit configured to determine a usage characteristic of a nonvolatile memory device; and

a background reference positioning circuit coupled to the status circuit and configured to perform, upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, background reads of representative pages of each page group of the closed block by sending threshold voltage shift read instructions to the nonvolatile memory device, the threshold voltage shift read instructions representative of offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block;

a read circuit coupled to the status circuit and to the background reference positioning circuit and configured to determine whether the usage characteristic meets a usage characteristic threshold and when the usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent host-requested reads of pages of the closed block by sending threshold voltage shift read instructions to the nonvolatile memory device, the threshold voltage shift read instructions using the set of updated threshold voltage offset values corresponding to the page group of the page being read;

wherein the status circuit is operable to determine a number of reads for each closed block of the nonvolatile memory device and the background reference positioning circuit is configured to determine that the read disturb event has occurred each time that the number of reads reaches a read disturb threshold; and

wherein the status circuit is operable to determine closed block retention time for each closed block of the nonvolatile memory device, and wherein the background reference positioning circuit is configured to determine that the retention timer event has occurred when the closed block retention time reaches a threshold retention time.

2. The nonvolatile memory controller of claim 1 further comprising a memory storage configured to store a background reference positioning table that includes each of the identified sets of updated threshold voltage offset values and corresponding index values and wherein the read circuit is configured to identify threshold voltage offset values to be used in the subsequent host-requested reads by indexing the background reference positioning table using an index value corresponding to the page group of the page being read.

3. The nonvolatile memory controller of claim 1 further comprising a memory storage configured to store a plurality of local reference positioning correction values, the nonvolatile memory controller further comprising:

a local reference positioning circuit coupled to the read circuit and operable to add one of the local reference positioning correction values to each of the threshold voltage offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a first set of local reference positioning offset values; and

wherein the read circuit is operable upon a first decode failure to read the failed page using the first set of local reference positioning offset values.

4. The nonvolatile memory controller of claim 3 wherein the local reference positioning correction values include an endurance correction value, a retention timing correction value and a read disturb correction value, and wherein the local reference positioning circuit is operable to add one of the local reference positioning correction values to each of the threshold voltages in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain the first set of local reference positioning threshold voltage offset values and further wherein the local reference positioning circuit is operable to add a different one of the endurance correction value, the retention timing correction value and the read disturb correction value to each of the offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a second set of local reference positioning threshold voltage offset values, and further wherein the read circuit is operable upon a second decode failure to read the failed page using the second set of local reference positioning offset values.

5. The nonvolatile memory controller of claim 2 wherein the usage characteristic comprises a number of program and erase cycles.

6. The nonvolatile memory controller of claim 1 wherein blocks of the nonvolatile memory device are grouped into a plurality of block groups and wherein pages within each block group are grouped into a plurality of page groups.

7. The nonvolatile memory controller of claim 2 wherein the status circuit is operable to determine a number of program and erase cycles for each block of the nonvolatile memory device and wherein the background reference positioning circuit is configured to determine that an endurance event has occurred each time that the determined number of program and erase cycles of the closed block reaches a threshold number of program and erase cycles.

8. The nonvolatile memory controller of claim 1 wherein the nonvolatile memory controller is configured to store, for each page group, a set of endurance threshold voltage offset values and a set of retention-read threshold voltage offset values, wherein the read circuit is configured to perform subsequent host-requested reads on blocks that are closed using the set of retention-read threshold voltage offset values corresponding to the page group of the page being read, and the read circuit is configured to perform subsequent host-requested reads on blocks that are not closed using the set of endurance threshold voltage offset values corresponding to the page group of the page being read.

9. The nonvolatile memory controller of claim 1 wherein the offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block further comprise starting reference threshold voltage offsets, the background reads of representative pages of each page group of the closed block performed by sending threshold voltage shift read instructions to the nonvolatile memory device, the threshold voltage shift read instructions representative of offsets to each of the plurality of starting reference threshold voltage offsets.

10. The nonvolatile memory controller of claim 9 further comprising:

wherein the nonvolatile memory controller is configured to store, for each page group, a set of endurance threshold voltage offset values and a set of retention-read threshold voltage offset values;

wherein, each time that an endurance event occurs, the background reference positioning circuit is configured to store the resulting updated threshold voltage offset values as the set of endurance threshold voltage offset values and as the set of retention-read threshold voltage offset values;

wherein, each time that a read disturb event occurs, the background reference positioning circuit is configured to store the resulting updated threshold voltage offset values as the set of retention-read threshold voltage offset values;

wherein, each time that a retention timer event occurs, the background reference positioning circuit is configured to store the resulting updated threshold voltage offset values as the set of retention-read threshold voltage offset values;

wherein, when updated threshold voltage offset values are determined in response to the occurrence of both an endurance event and one or more of a read disturb event and a retention timer event, the background reference positioning circuit is configured to store the resulting updated threshold voltage offset values as the set of endurance threshold voltage offset values and as the set of retention-read threshold voltage offset values;

wherein, when an endurance event occurs, the stored set of endurance threshold voltage offset values are used as the starting reference threshold voltage offsets in the corresponding background reads;

wherein, when a retention timer event occurs, the background reference positioning circuit is configured to use the stored set of retention-read threshold voltage offset values as starting reference threshold voltage offsets in the corresponding background reads;

wherein, when a read disturb event occurs, the stored set of retention-read threshold voltage offset values are used as the starting reference threshold voltage offsets in the corresponding background reads; and

wherein, each time that a block erase occurs, the stored set of endurance threshold voltage offset values are used as the starting reference threshold voltage offsets in the following background reads.

11. The nonvolatile memory controller of claim 1 wherein the nonvolatile memory controller is configured to store, for each page group, a set of endurance threshold voltage offset values and a set of retention-read threshold voltage offset values, and wherein, when the subsequent host-requested read is performed in a block that is closed, the read is performed using the set of retention-read threshold voltage offset values, and further wherein, when the subsequent host-requested read is performed in a block that is not closed, the read is performed using the set of endurance threshold voltage offset values.

12. A nonvolatile memory system comprising:

a plurality of nonvolatile memory devices;

a memory controller coupled to each of the nonvolatile memory devices, the memory controller configured to perform program operations and read operations on memory cells of the nonvolatile memory devices, the nonvolatile memory controller comprising;

a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device;

a background reference positioning circuit coupled to the status circuit and configured to perform, upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, background reads of representative pages of each page group of the closed block by sending threshold voltage shift read instructions to the nonvolatile memory device to be read, the threshold voltage shift read instructions representative of offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block; and

a read circuit coupled to the status circuit and to the background reference positioning circuit and configured to determine whether a usage characteristic meets a usage characteristic threshold and when the usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent host-requested reads of pages of the closed block by sending threshold voltage shift read instructions to the nonvolatile memory device to be read, the threshold voltage shift read instructions using the set of updated threshold voltage offset values corresponding to the page group of the page being read; and

wherein the status circuit is operable to determine a number of reads for each closed block of the nonvolatile memory device and the background reference positioning circuit is configured to determine that a read disturb event has occurred each time that the number of reads for a particular closed block reaches a read disturb threshold; and

wherein the status circuit is operable to determine closed block retention time for each closed block of the nonvolatile memory device, and wherein the background reference positioning circuit is configured to determine that a retention timer event has occurred each time that the closed block retention time reaches a threshold retention time.

13. The nonvolatile memory system of claim 12 further comprising:

memory storage configured to store a background reference positioning table that includes threshold voltage shift read parameters for each page group of a plurality of page groups in each block of a nonvolatile memory device and corresponding index values; and

wherein the read circuit is configured to perform the subsequent host-requested reads of pages of the closed block using a threshold voltage shift read instruction that indicates threshold voltage shift read parameters for the page group of the page being read and further wherein the background reference positioning circuit is configured to store the sets of updated threshold voltage offset values in the respective threshold voltage shift read parameters for each page group of the closed block.

14. The nonvolatile memory system of claim 13 wherein a local reference positioning table that includes local reference positioning correction values is stored in the memory storage, the nonvolatile memory controller further comprising:

a local reference positioning circuit coupled to the read circuit and coupled to the memory storage, the local reference positioning circuit operable to add one of the local reference positioning correction values to each of the updated threshold voltage offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to calculate a first set of local reference positioning threshold voltage offset values, and operable to add a different one of the local reference positioning correction values to each of the updated threshold voltage offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to calculate a second set of local reference positioning threshold voltage offset values; and

wherein the read circuit is operable upon a first decode failure to read the failed page using the first set of local reference positioning threshold voltage offset values and is operable upon a second decode failure to read the failed page using the second set of local reference positioning threshold voltage offset values.

15. The nonvolatile memory system of claim 14 wherein the local reference positioning correction values include a first local reference positioning correction value that is used to calculate the first set of local reference positioning threshold voltage offset values, a second local reference positioning correction value that is used to calculate the second set of local reference positioning threshold voltage offset values and a third local reference positioning correction value, and wherein the local reference positioning circuit is operable to add the third local reference positioning correction value to each of the updated threshold voltage offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a third set of local reference positioning threshold voltage offset values, and wherein the read circuit is operable upon a third decode failure to read the failed page using the third set of local reference positioning threshold voltage offset values.

16. The nonvolatile memory system of claim 15 wherein the local reference positioning correction values include an endurance correction value, a retention timing correction value and a read disturb correction value, and wherein the local reference positioning circuit is operable to determine the order in which the endurance correction value, the retention timing correction value and the read disturb correction value are to be applied to decode failures based on the current retention time, the current number of reads and the current number of program and erase cycles.

17. A method for reducing latency of a nonvolatile memory controller comprising:

identifying a plurality of page groups in each block of a nonvolatile memory device;

performing background reads of representative pages of each page group of a block using threshold voltage shift read instructions representative of offsets to each threshold voltage that is required for reading the representative pages of each page group of the block to identify a set of updated threshold voltage offset values for each page group of the block;

storing a local reference positioning table that includes a plurality of local reference positioning correction values;

determining the order in which the plurality of local reference positioning correction values are to be applied to decode failures by determining whether a current number of program and erase cycles is near a next endurance threshold, determining whether a current read count is near a next read disturb threshold and determining whether a current retention time is near a next retention time threshold;

based on the determined order, adding a first one of the local reference positioning correction values to each of the threshold voltage offset values in the set of updated threshold voltage offset values to obtain a first set of local reference positioning threshold voltage offset values;

based on the determined order, adding a second one of the local reference positioning correction values to each of the threshold voltage offset values in the set of updated threshold voltage offset values to obtain a second set of local reference positioning threshold voltage offset values;

based on the determined order, adding a third one of the local reference positioning correction values to each of the threshold voltage offset values in the set of updated threshold voltage offset values to obtain a third set of local reference positioning threshold voltage offset values;

upon a first decode failure of a read of one of the representative pages, reading the one of the representative pages using the first set of local reference positioning threshold voltage offset values;

upon a second decode failure of a read of the one of the representative pages, reading the one of the representative pages using the second set of local reference positioning threshold voltage offset values; and

upon a third decode failure of a read of the one of the representative pages, reading the one of the representative pages using the third set of local reference positioning threshold voltage offset values.

18. The method of claim 17

wherein the background reads are performed upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, and wherein the offsets to each threshold voltage that is required for reading the representative pages of each page group of the block further comprise starting reference threshold voltage offsets, the background reads of representative pages of each page group of the block performed by sending threshold voltage shift read instructions at offsets to each of a plurality of starting reference threshold voltage offsets.

19. The method of claim 18 further comprising:

identifying for each page group a set of endurance threshold voltage offset values and a set of retention-read threshold voltage offset values;

wherein, when an endurance event occurs, the resulting updated threshold voltage offset values are stored as the set of endurance threshold voltage offset values and are stored as the set of retention-read threshold voltage offset values;

wherein, when a read disturb event occurs, the resulting updated threshold voltage offset values are stored as the set of retention-read threshold voltage offset values;

wherein, when a retention timer event occurs, the resulting updated threshold voltage offset values are stored as the set of retention-read threshold voltage offset values;

wherein, when updated threshold voltage offset values are determined in response to the occurrence of both an endurance event and one or more of a read disturb event and a retention timer event, the resulting updated threshold voltage offset values are stored as the set of endurance threshold voltage offset values and are stored as the set of retention-read threshold voltage offset values;

wherein, when an endurance event occurs, the stored set of endurance threshold voltage offset values are used as the starting reference threshold voltage offsets in the corresponding background reads;

wherein, when a retention timer event occurs, the stored set of retention-read threshold voltage offset values are used as the starting reference threshold voltage offset in the corresponding background reads;

wherein, when a read disturb event occurs, the stored set of retention-read threshold voltage offset values are used as the starting reference threshold voltage offset in the corresponding background reads; and

wherein, each time that a block erase occurs, the stored set of endurance threshold voltage offset values are used as the starting reference threshold voltage offset in the following background reads.

20. The method of claim 17 further comprising:

identifying a block group;

storing the set of updated threshold voltage offset values for each page group of the closed block as a set of updated threshold voltage offset values for each page group of the block group that includes the closed block; and

wherein the identifying a plurality of page groups in each block of a nonvolatile memory device further includes identifying a plurality of page groups in each block group.