Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices

• US 10,157,769 B2
• Filed: 04/06/2017
• Issued: 12/18/2018
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Zhang, Ming
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): Jones, Eric W
• Application Number:
  US15/481,301
• Publication Number:
  US 20170213761A1
• Time in Patent Office: 621 Days
• Field of Search: 438106, 438110, 438118, 438119, 438455, 438459, 438514, 438527, 257506
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.

Claims

1. A method for fabricating a semiconductor device, comprising:

providing a first semiconductor substrate;

forming a first insulator material over the first semiconductor substrate;

providing a second semiconductor substrate comprising a single crystalline silicon material having a first doped region and a second doped region;

forming a conductive material over the second semiconductor substrate;

forming an amorphous adhesion material over and in direct contact with the conductive material, the amorphous adhesion, material comprising one or both of amorphous silicon and amorphous germanium; and

bonding the first and second substrates, to each other, the bonding comprising positioning the amorphous adhesion material directly against the insulator material over the first semiconductor substrate.

2. The method of claim 1 further comprising forming a top electrode, a memory medium, and a bottom electrode over the second semiconductor substrate.

3. The method of claim 2 further comprising removing a first portion of the top electrode, the memory medium, the bottom electrode, the second semiconductor substrate, the conductive material, and the adhesion material to form at least one conductive strap having a pillar of the top electrode, the memory medium, the bottom electrode and the second semiconductor substrate thereon.

4. The method of claim 3 further comprising removing another portion of the top electrode, the memory medium, the bottom electrode, and the second semiconductor substrate to form at least one diode over the at least one conductive strap having a memory cell on the at least one diode.

5. A method for fabricating a semiconductor device, comprising:

forming an insulator material on d first semiconductor substrate;

forming a conductive material and an adhesion material overlying a second semiconductor substrate;

positioning the insulator material on the first semiconductor substrate in direct contact with the adhesion material and bonding the adhesion material of the second substrate to the insulator material to forma base comprising the first and second semiconductor substrates;

forming a first doped region and a second doped region within a monocrystalline silicon material of the second semi conductor substrate;

forming a bottom electrode over the second semiconductor substrate;

removing a first portion of the bottom electrode, the second semiconductor substrate, the conductive material, and the adhesion material to form at least one conductive strap having a pillar of the bottom electrode and the second semiconductor substrate thereon; and

removing a second portion of the bottom electrode and the second semiconductor substrate to form at least one diode over the at least one conductive strap wherein a portion of the bottom electrode overlies the at least one diode; and

forming a memory medium over each portion of the bottom electrode.

6. The method of claim 5, further comprising

doping the precursor semiconductor substrate to form the first doped region proximate the conductive material and the second doped region adjacent the first doped region;

implanting ions into the second doped region of the precursor semiconductor substrate to form an implanted zone therein; and

removing a portion of the precursor semiconductor substrate proximate the implanted zone of the precursor semiconductor substrate.

7. The method of claim 5, further comprising forming a bit line in electrical communication with the memory cell on the at least one diode.

8. The method of claim 5, further comprising forming a logic device on the first semiconductor substrate.

9. The method of claim 5, wherein removing the first portion of the top electrode, the memory medium, the bottom electrode, the second semiconductor substrate, the conductive material, and the adhesion material to form at least one conductive strap having a pillar of the top electrode, the memory medium, the bottom electrode and the semiconductor substrate thereon comprises forming a plurality of trenches extending in a direction parallel to the pillar.

10. The method of claim 5, wherein removing the second portion of the top electrode, the memory medium, the bottom electrode, and the second semiconductor substrate to form at least one diode over the at least one conductive strap having a memory cell on the at least one diode comprises removing another portion of the top electrode, the memory medium, the bottom electrode, and the second semiconductor substrate in a second direction substantially perpendicular to the pillar.

11. The method of claim 5 wherein the adhesion material is amorphous and comprises at least one of amorphous silicon and amorphous germanium.

12. A method of forming a semiconductor device, comprising:

providing a first substrate comprising an insulator material;

providing a second substrate comprising a conductive material;

forming an amorphous adhesion material over the conductive material;

forming a bonded structure by inverting the second substrate over the first substrate such that the amorphous adhesion material directly contacts the insulator material;

forming trenches through the second substrate;

forming at least one diode over the conductive material in the bonded structure.

13. The method of claim 12 wherein the at least one diode comprises a first doped region overlying the conductive region and a second doped region overlying the first doped region, the conductivity of the first doped region being opposite the conductivity of the second doped region.

14. The method of claim 13 further comprising, forming a memory cell over the second doped region.

15. The method of claim 12 wherein the amorphous adhesion material comprises one or both of amorphous silicon and amorphous germanium.

16. The method of claim 12 wherein the at least one diode comprises a single crystalline silicon material over the conductive material in the bonded structure.

17. The method of claim 12 wherein the at least one diode has a width of less than about 20 nm.