Method for forming chip package involving cutting process

• US 10,157,846 B2
• Filed: 10/13/2016
• Issued: 12/18/2018
• Est. Priority Date: 10/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shing-Chao, Lin, Chih-Wei, Chiang, Tsung-Hsien, Cheng, Ming-Da, Hsieh, Ching-Hua
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US15/292,762
• Publication Number:
  US 20180108613A1
• Time in Patent Office: 796 Days
• Field of Search: None
• CPC Class Codes: B29C 45/14639 for obtaining an insulating effect, e.g. for electrical components
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices

Abstract

Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

Claims

1. A method for forming a chip package, comprising:

disposing a semiconductor die over a carrier substrate;

forming a protection layer over the carrier substrate to surround the semiconductor die;

forming a dielectric layer over the protection layer and the semiconductor die;

cutting an upper portion of the dielectric layer to reduce a roughness of the dielectric layer; and

forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

2. The method for forming a chip package as claimed in claim 1, further comprising:

disposing a mold over the carrier substrate, wherein the protection layer is formed between the mold and the carrier substrate after the mold is disposed; and

removing the mold after the protection layer is formed.

3. The method for forming a chip package as claimed in claim 2, further comprising injecting a molding compound material into the mold to form the protection layer.

4. The method for forming a chip package as claimed in claim 2, further comprising forming a conductive pillar over the carrier substrate before the mold is disposed over the carrier substrate.

5. The method for forming a chip package as claimed in claim 4, further comprising patterning the dielectric layer to form an opening exposing the conductive pillar, wherein after the conductive layer is formed, the conductive layer is electrically connected to the conductive pillar through the opening.

6. The method for forming a chip package as claimed in claim 5, wherein the dielectric layer is patterned to form the opening after the upper portion of the dielectric layer is cut.

7. The method for forming a chip package as claimed in claim 2, wherein the semiconductor die has a conductive feature, and the method further comprises:

patterning the dielectric layer to form an opening exposing the conductive feature of the semiconductor die, wherein after the conductive layer is formed, the conductive layer is electrically connected to the conductive feature through the opening.

8. The method for forming a chip package as claimed in claim 7, wherein the dielectric layer is patterned to form the opening after the upper portion of the dielectric layer is cut.

9. The method for forming a chip package as claimed in claim 1, further comprising:

forming a second dielectric layer over the dielectric layer and the conductive layer; and

forming a second conductive layer over the second dielectric layer such that the second conductive layer is electrically connected to the conductive layer.

10. The method for forming a chip package as claimed in claim 1, wherein cutting scratches are formed on a surface of the dielectric layer by cutting the upper portion of the dielectric layer.

11. A method for forming a chip package, comprising:

forming a molding compound layer to surround a semiconductor die;

forming a dielectric layer over the molding compound layer and the semiconductor die;

partially cutting the dielectric layer such that a roughness of the dielectric layer is reduced; and

forming a conductive layer over the dielectric layer after the dielectric layer is substantially planarized.

12. The method for forming a chip package as claimed in claim 11, wherein the semiconductor die has a conductive feature, and the method further comprises:

patterning the dielectric layer to form an opening exposing the conductive feature of the semiconductor die, wherein after the conductive layer is formed, the conductive layer is electrically connected to the conductive feature through the opening.

13. The method for forming a chip package as claimed in claim 12, wherein the dielectric layer is patterned to form the opening after the dielectric layer is partially cut.

14. The method for forming a chip package as claimed in claim 12, wherein the dielectric layer is patterned to form the opening before the dielectric layer is partially cut.

15. A method for forming a chip package, comprising:

forming a protection layer to surround a semiconductor die and a conductive structure next to the semiconductor die;

forming a dielectric layer over the protection layer, the semiconductor die, and the conductive structure;

cutting an upper portion of the dielectric layer such that a roughness of the dielectric layer is reduced; and

forming a conductive layer over the dielectric layer, wherein the conductive layer is electrically connected to the conductive structure.

16. The method for forming a chip package as claimed in claim 15, wherein the formation of the protection layer comprises:

disposing a mold over the semiconductor die and the conductive structure, wherein the mold comprises a release film; and

injecting a molding compound material into the mold through an opening of the mold to form the protection layer, wherein the release film is in direct contact with the semiconductor die during the injecting of the molding compound material.

17. The method for forming a chip package as claimed in claim 15, further comprising patterning the dielectric layer to form an opening exposing the conductive structure after cutting the upper portion of the dielectric layer and before the formation of the conductive layer.

18. The method for forming a chip package as claimed in claim 15, further comprising patterning the dielectric layer to form an opening exposing the conductive structure before cutting the upper portion of the dielectric layer and before the formation of the conductive layer.

19. The method for forming a chip package as claimed in claim 15, further comprising cutting an upper portion of the conductive structure before the protection layer is formed.

20. The method for forming a chip package as claimed in claim 15, wherein a top surface of the conductive structure is below a top surface of the dielectric layer after cutting the upper portion of the dielectric layer.