Semiconductor structure and manufacturing method thereof

• US 10,157,900 B2
• Filed: 12/15/2016
• Issued: 12/18/2018
• Est. Priority Date: 10/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Shih-Wei, Pan, Hsin-Yu, Wu, Kai-Chiang, Yang, Ching-Feng, Liu, Ming-Kai, Miao, Chia-Chun
• Primary Examiner(s): DINKE, BITEW A
• Application Number:
  US15/380,821
• Publication Number:
  US 20170098640A1
• Time in Patent Office: 733 Days
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/17519 : including bump connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2101 : Structure
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/24105 : Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24146 : the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/24225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/80815 : Reflow soldering
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92124 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 25/065 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Claims

1. A method of manufacturing a semiconductor structure, the method comprising:

bonding a semiconductor die to a substrate, the substrate having circuitry thereon;

forming a conductive plug with a first end connected to the substrate;

disposing a molding compound on the substrate;

after disposing the molding compound on the substrate, exposing a contact area of a passive surface of the semiconductor die and a contact area of a second end of the conductive plug, wherein the passive surface, the second end, and a surface of the molding compound are at a first same level; and

after exposing, forming a metal structure on the passive surface of the semiconductor die and the second end of the conductive plug, the metal structure comprising an active portion including a first recess with a first active portion contact area below the first recess and a dummy portion including a second recess with a first dummy portion contact area below the second recess, wherein the forming the metal structure comprises;

depositing the active portion on the conductive plug with the first active portion contact area being in contact with the contact area of the second end of the conductive plug, the active portion being electrically coupled with the circuitry through the conductive plug; and

depositing the dummy portion on the semiconductor die with the first dummy portion contact area being in contact with the contact area of the passive surface of the semiconductor die and not being electrically coupled with any circuitry.

2. The method of claim 1, wherein disposing the molding compound on the substrate comprises the molding compound surrounding the semiconductor die and the conductive plug.

3. The method of claim 2, further comprising performing a grinding operation to remove a portion of the molding compound to expose the passive surface of the semiconductor die and the second end of the conductive plug.

4. The method of claim 1, further comprising disposing a dummy bump on a portion of the metal structure.

5. The method of claim 1, wherein the substrate comprises a post-passivation interconnect (PPI).

6. The method of claim 1, wherein forming the conductive plug comprises forming a patterned photo resist on the substrate.

7. A method of forming a semiconductor device, the method comprising:

forming a conductive pillar on a substrate;

bonding a first integrated circuit to the substrate;

forming a molding compound between the first integrated circuit and the conductive pillar;

forming an insulating layer over the molding compound, a first side of the insulating layer facing towards the molding compound and a second side of the insulating layer facing away from the molding compound;

etching the insulating layer to expose a contact area of a passive surface of the first integrated circuit;

forming a metal structure over the insulating layer, wherein the metal structure comprises a dummy portion and an active portion, including;

depositing material of the active portion comprising a single, continuous material extending from the conductive pillar to an uppermost surface of the metal structure, the active portion being electrically coupled to the conductive pillar; and

depositing material of the dummy portion on the second side of the insulating layer and in physical contact with the contact area of the passive surface of the first integrated circuit, wherein the dummy portion is not electrically coupled to the first integrated circuit or the substrate.

8. The method of claim 7, wherein the substrate comprises a second integrated circuit.

9. The method of claim 7, wherein forming the conductive pillar is performed before bonding the first integrated circuit to the substrate.

10. The method of claim 7, further comprising thinning the molding compound to expose the first integrated circuit.

11. The method of claim 7, wherein the dummy portion directly contacts the first integrated circuit.

12. The method of claim 7, further comprising forming an external connection to the dummy portion.

13. The method of claim 12, wherein the external connection comprises a solder connection.

14. The method of claim 7, wherein bonding the first integrated circuit to the substrate comprises flip-chip bonding.

15. A method of forming a semiconductor device, the method comprising:

forming a first insulating layer over a molding compound and a first integrated circuit, a passive surface of the first integrated circuit and a conductive plug being exposed in the first insulating layer;

forming a dummy conductive portion over the first insulating layer, the dummy conductive portion extending through a first opening in the first insulating layer, wherein the dummy conductive portion comprises a single, continuous material that extends through the first insulating layer, and wherein the dummy conductive portion is electrically isolated from active circuitry;

forming an active conductive portion over the first insulating layer, the active conductive portion extending through a second opening in the first insulating layer, the active conductive portion being electrically coupled to the conductive plug;

flowing a soldering material onto a contact area surface of a dummy metallization layer that is electrically coupled to the dummy conductive portion to form a first conductive external connector electrically coupled to the dummy conductive portion, the first conductive external connector covering the contact area surface and a separate sidewall surface portion of the dummy metallization layer; and

forming a second conductive external connector electrically coupled to the active conductive portion.

16. The method of claim 15, wherein the dummy conductive portion directly contacts the first integrated circuit.

17. The method of claim 15, further comprising, prior to forming the first insulating layer, electrically coupling the first integrated circuit to a substrate.

18. The method of claim 17, wherein the substrate comprises a second integrated circuit.

19. The method of claim 15, wherein the first conductive external connector and the second conductive external connector comprise solder connections.

20. The method of claim 15, further comprising, prior to forming the first insulating layer:

forming the molding compound over the first integrated circuit and the conductive plug; and

thinning the molding compound to expose the first integrated circuit and the conductive plug.