3D semiconductor device and structure

• US 10,157,909 B2
• Filed: 01/04/2018
• Issued: 12/18/2018
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/862,616
• Publication Number:
  US 20180190811A1
• Time in Patent Office: 348 Days
• Field of Search: None
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

Claims

1. A 3D semiconductor device, the device comprising:

a first layer comprising first transistors each comprising a silicon channel;

a second layer comprising second transistors each comprising a silicon channel, said second layer overlaying said first transistors,

wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and

a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer underlying said first transistors,

wherein a plurality of said third transistors form a logic circuit, and

wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error,

wherein said first layer thickness is less than one micron, and

wherein said first transistors are junction-less transistors.

2. The 3D semiconductor device according to claim 1,

wherein said second transistors comprise a polysilicon channel.

3. The 3D semiconductor device according to claim 1,

wherein said first layer comprises a non-volatile memory cell.

4. The 3D semiconductor device according to claim 1,

wherein said first layer comprises side-gate transistors.

5. The 3D semiconductor device according to claim 1,

wherein said self-aligned is a visible result of at least two vertically stacked structures being processed together following a single lithography step.

6. The 3D semiconductor device according to claim 1, further comprising:

periphery circuits,

wherein said periphery circuits comprise said logic circuit.

7. The 3D semiconductor device according to claim 1,

wherein at least one of said first transistors are directly connected to at least one of said second transistors.

8. A 3D semiconductor device, the device comprising:

a first layer comprising first transistors each comprising a silicon channel;

a second layer comprising second transistors each comprising a silicon channel, said second layer overlaying said first transistors,

wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and

a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer underlying said first transistors,

wherein a plurality of said third transistors form a logic circuit,

wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error, and

wherein said first transistors are junction-less transistors.

9. The 3D semiconductor device according to claim 8,

wherein said second layer thickness is less than one micron.

10. The 3D semiconductor device according to claim 8,

wherein said first layer comprises a floating body memory cell.

11. The 3D semiconductor device according to claim 8,

wherein said first layer comprises independently addressable double-gate transistors.

12. The 3D semiconductor device according to claim 8,

wherein said first layer thickness is less than one micron.

13. The 3D semiconductor device according to claim 8,

wherein said 3D semiconductor device comprises an electrically modifiable resistive element.

14. The 3D semiconductor device according to claim 8,

wherein at least one of said first transistors are directly connected to at least one of said second transistors.

15. A 3D semiconductor device, the device comprising:

a first layer comprising first transistors each comprising a silicon channel;

a second layer comprising second transistors each comprising a silicon channel, said second layer overlaying said first transistors,

wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and

a third layer comprising third transistors each comprising a single crystal silicon channel, said third structure underlying said first transistors,

wherein a plurality of said third transistors form a logic circuit,

wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error,

wherein said first layer thickness is less than one micron, and

wherein said second transistors are junction-less transistors.

16. The 3D semiconductor device according to claim 15,

wherein said second layer thickness is less than one micron.

17. The 3D semiconductor device according to claim 15,

wherein said first layer comprises a floating body memory cell.

18. The 3D semiconductor device according to claim 15,

wherein said first layer comprises independently addressable double-gate transistors.

19. The 3D semiconductor device according to claim 15,

wherein said 3D semiconductor device comprises an electrically modifiable resistive element.

20. The 3D semiconductor device according to claim 15,

wherein at least one of said first transistors are directly connected to at least one of said second transistors.