Semiconductor device including memory cell which includes transistor and capacitor

• US 10,157,939 B2
• Filed: 05/11/2017
• Issued: 12/18/2018
• Est. Priority Date: 07/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US15/592,687
• Publication Number:
  US 20170250205A1
• Time in Patent Office: 586 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0733 in combination with capacitors only
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time. Another object is to increase the degree of integration of a semiconductor device and to increase the storage capacity per unit area. A semiconductor device is formed with a material capable of sufficiently reducing off-state current of a transistor, such as an oxide semiconductor material that is a wide-bandgap semiconductor. With the use of a semiconductor material capable of sufficiently reducing off-state current of a transistor, the semiconductor device can hold data for a long time. Furthermore, a wiring layer provided under a transistor, a high-resistance region in an oxide semiconductor film, and a source electrode are used to form a capacitor, thereby reducing the area occupied by the transistor and the capacitor.

Claims

1. A semiconductor device comprising a memory cell, the memory cell comprising a transistor and a capacitor,

wherein the transistor comprises:

an oxide semiconductor film;

a first electrode layer and a second electrode layer over the oxide semiconductor film;

a gate insulating film over the oxide semiconductor film; and

a gate electrode layer over the gate insulating film,

wherein the capacitor comprises;

part of the oxide semiconductor film;

an insulating film over the part of the oxide semiconductor film; and

the second electrode layer over the insulating film,

wherein the part of the oxide semiconductor film, the insulating film of the capacitor, and the second electrode layer of the capacitor overlap with each other, and

wherein the gate insulating film of the transistor is separated from the insulating film of the capacitor.

2. The semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises a channel formation region, a pair of first regions with the channel formation region therebetween, and a pair of second regions with the channel formation region therebetween,

wherein one of the pair of first regions and one of the pair of second regions are stacked, and

wherein the other of the pair of first regions and the other of the pair of second regions are stacked.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises a channel formation region, a pair of first regions with the channel formation region therebetween, and a pair of second regions with the channel formation region therebetween,

wherein one of the pair of first regions and one of the pair of second regions are stacked,

wherein the other of the pair of first regions and the other of the pair of second regions are stacked, and

wherein a resistance value of the pair of first regions is higher than a resistance value of the pair of second regions.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises indium and zinc.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises a carrier concentration being less than or equal to 1×

10¹²/cm³.

6. The semiconductor device according to claim 1, wherein the part of the oxide semiconductor film of the capacitor and the insulating film of the capacitor function as a dielectric of the capacitor.

7. The semiconductor device according to claim 1, wherein the capacitor further comprises a third electrode layer below a bottom surface of the part of the oxide semiconductor film of the capacitor.