Cross-point memory and methods for fabrication of same

• US 10,157,965 B2
• Filed: 01/04/2017
• Issued: 12/18/2018
• Est. Priority Date: 02/25/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sciarrillo, Samuele
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US15/398,475
• Publication Number:
  US 20170186816A1
• Time in Patent Office: 713 Days
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

Claims

1. A method, comprising:

forming a memory cell line stack extending in a first direction, comprising;

forming a memory cell material stack comprising a storage element material and a selector element material;

patterning the memory cell material stack to form the memory cell line stack comprising a storage material line and a selector material line;

forming a protective dielectric material on portions of sidewalls of the memory cell line stack, comprising;

forming an initial protective dielectric material covering the memory cell line stack; and

removing a portion of the initial protective dielectric material to expose sidewalls of one of the storage material line or the selector material line while leaving the initial protective dielectric material on at least portions of the sidewalls of the other of the storage material line or the selector material line.

2. The method of claim 1, further comprising:

cleaning the exposed portions of sidewalls of the one of the storage material line or the selector material line, while continuing to protect the sidewalls of the other of the storage material line or the selector material line with the initial protective dielectric material.

3. The method of claim 2, wherein removing the portion of the initial protective dielectric material comprises exposing sidewalls of the storage material line while leaving the initial protective dielectric material on at least portions of the sidewalls of the selector material line.

4. The method of claim 2, wherein the memory cell line stack is a phase change memory device, and wherein a first element material comprises a first chalcogenide composition and a second element material comprises a second chalcogenide composition.

5. The method of claim 4, wherein the first chalcogenide composition comprises As, Se, or a combination thereof.

6. The method of claim 5, wherein cleaning comprises removing As material or Se material from exposed sidewalls of the storage material line.

7. The method of claim 1, further comprising:

forming a first electrode between the selector element material and a first conductive line;

forming a second electrode between the selector element material and the storage element material; and

forming a third electrode between the storage element material and a second conductive line.

8. The method of claim 7, wherein the first conductive line is formed in a second direction and the second conductive line is formed in a third direction different from the second direction.

9. The method of claim 8, wherein the second direction is orthogonal to the third direction.

10. A method, comprising:

forming a first protective dielectric material over sidewalls of a lower line memory cell stack;

etching a portion of the first protective dielectric material in a first direction;

filling a region between the lower line memory cell stack and a second lower line memory cell stack with a first isolation dielectric material after etching the portion;

depositing a conductive material over the first isolation dielectric material;

etching a portion of the lower line memory cell stack and the conductive material in the first direction; and

forming a second protective dielectric material over sidewalls of an unetched portion of the lower line memory cell stack and the conductive material.

11. The method of claim 10, further comprising:

forming a first hard mask material over a memory cell stack; and

forming an etch mask line pattern based at least in part on etching the memory cell stack and the first hard mask material, wherein the lower line memory cell stack is formed based at least in part on forming the etch mask line pattern.

12. The method of claim 11, further comprising:

forming a lower electrode material over a conductive layer;

forming a selector element material over the lower electrode material;

forming a middle electrode material over the selector element material;

forming a storage element material over the middle electrode material; and

forming an upper electrode material over the storage element material.

13. The method of claim 11, wherein the first hard mask material comprises a dielectric material.

14. The method of claim 10, wherein the etched portion of the lower line memory cell stack extends in the first direction.

15. The method of claim 10, wherein forming the first protective dielectric material comprises uniformly depositing the first protective dielectric material over the lower line memory cell stack.

16. The method of claim 10, wherein forming the second protective dielectric material comprises uniformly depositing the second protective dielectric material over the unetched portion of the lower line memory cell stack.

17. The method of claim 10, wherein the second protective dielectric material is in contact with an upper surface of the first protective dielectric material.

18. The method of claim 10, further comprising:

performing a first etching process in the first direction associated with the first protective dielectric material; and

performing a second etching process in the first direction associated with the second protective dielectric material.