FinFETs with strained well regions
First Claim
1. A device comprising:
- a substrate;
insulation regions over a portion of the substrate;
a first semiconductor region between the insulation regions;
a second semiconductor region over and adjoining the first semiconductor region, wherein the second semiconductor region comprises an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin;
a third semiconductor region over the semiconductor fin, wherein the third semiconductor region comprises at least a first sub layer doped with an n-type impurity, wherein the first, the second and the third semiconductor regions are formed of different materials;
a silicon cap over the third semiconductor region, wherein the silicon cap is free from n-type and p-type impurities; and
a source region and a drain region on opposite sides of the semiconductor fin.
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Abstract
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
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Citations
20 Claims
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1. A device comprising:
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a substrate; insulation regions over a portion of the substrate; a first semiconductor region between the insulation regions; a second semiconductor region over and adjoining the first semiconductor region, wherein the second semiconductor region comprises an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin; a third semiconductor region over the semiconductor fin, wherein the third semiconductor region comprises at least a first sub layer doped with an n-type impurity, wherein the first, the second and the third semiconductor regions are formed of different materials; a silicon cap over the third semiconductor region, wherein the silicon cap is free from n-type and p-type impurities; and a source region and a drain region on opposite sides of the semiconductor fin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A device comprising:
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a silicon substrate; Shallow Trench Isolation (STI) regions extending into the silicon substrate; a semiconductor fin protruding higher than top surfaces of the STI regions, wherein the semiconductor fin is between opposite portions of the STI regions; a silicon germanium region contacting a top surface and sidewalls of the semiconductor fin, wherein the silicon germanium region comprises; a first sub layer having a first n-type impurity concentration; and a second sub layer over the first sub layer, wherein the second sub layer has a second n-type impurity concentration higher than the first n-type impurity concentration; a gate dielectric over the silicon germanium region; a gate electrode over the gate dielectric; and a source region and a drain region on opposite sides of the gate dielectric and the gate electrode, wherein the source region and the drain region are n-type regions, and wherein the silicon germanium region extends from the source region and the drain region. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A device comprising:
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a silicon germanium region comprising; a first layer having a first n-type impurity concentration; a second layer over the first layer, wherein the second layer has a second n-type impurity concentration; and a third layer over the second layer, wherein the third layer has a third n-type impurity concentration, and the second n-type impurity concentration is higher than both the first n-type impurity concentration and the third n-type impurity concentration; a gate dielectric over the silicon germanium region; a gate electrode over the gate dielectric; and a source region and a drain region on opposite sides of the gate dielectric and the gate electrode. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification