Low-latency low-uncertainty timer synchronization mechanism across multiple devices

• US 10,159,053 B2
• Filed: 08/30/2016
• Issued: 12/18/2018
• Est. Priority Date: 02/02/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Romera, Joaquin, Zethner, Graig, Khan, Raheel
• Primary Examiner(s): LO, DIANE LEE
• Application Number:
  US15/251,581
• Publication Number:
  US 20170223646A1
• Time in Patent Office: 840 Days
• Field of Search: None
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04W 52/0235 where the received signal is a power saving command
• CPC Class Codes: H04W 56/001 Synchronization between nodes
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

Claims

1. A method for synchronizing timing in devices coupled to a data communication link, comprising:

at a first device, receiving a first time value from a second device through the data communication link, the first time value corresponding to a future point in time;

at the first device, receiving a trigger signal from the second device through the data communication link;

loading the first time value into a timer of the first device, at a first-occurring edge in a first clock signal after the trigger signal is received, wherein the first clock signal is used to increment the timer; and

identifying to the second device a phase of the first clock signal at the time the trigger signal is received,

wherein the phase of the first clock signal at the time the trigger signal is received is indicative of a phase difference between first clock signal and a second clock signal that is used by the second device.

2. The method of claim 1, wherein the first time value is loaded into the timer in a cycle of the first clock signal that terminates at the first-occurring edge in the first clock signal.

3. The method of claim 1, further comprising:

sampling the trigger signal using a third clock signal that has a frequency that is more than twice the frequency of the first clock signal.

4. The method of claim 1, further comprising:

counting periods of an oversampling clock signal for the duration of each cycle of the first clock signal, wherein the oversampling clock signal has a frequency that is greater than the frequency of the first clock signal; and

identifying the phase of the first clock signal at the time the trigger signal is received by providing the second device with a number representing the periods of the oversampling clock signal counted from beginning of a clock cycle of the first clock signal until the trigger signal is received.

5. The method of claim 1, wherein the trigger signal is received before arrival of the future point in time.

6. The method of claim 1, comprising:

entering a low-power mode of operation after receiving the first time value; and

receiving the trigger signal while exiting the low-power mode of operation,

wherein the data communication link is inactive during the low-power mode of operation.

7. The method of claim 1, wherein the second clock signal is used by the second device to increment a system timer on the second device, and wherein the system timer defines system time for the devices coupled to the data communication link.

8. The method of claim 1, wherein the second clock signal is used by the second device to define system time, and wherein the second clock signal is half the frequency of the first clock signal.

9. The method of claim 8, wherein the phase of the first clock signal at the time the trigger signal is received indicates a difference between system time and a local time maintained by the timer.

10. The method of claim 1, wherein receiving the trigger signal comprises:

using a metastability-hardened flip-flop to receive the trigger signal from the data communication link.

11. An apparatus, comprising:

a data communication link;

a first device coupled to the data communication link and adapted to define system time; and

a second device coupled to the data communication link and having a timer adapted to track the system time, wherein the second device is configured to;

receive a first time value from the first device through the data communication link, the first time value corresponding to a future point in time;

receive a trigger signal from the first device through the data communication link;

load the first time value into the timer, at a first-occurring edge in a first clock signal after the trigger signal is received, wherein the first clock signal is used to increment the timer; and

identify to the first device a phase of the first clock signal at the time the trigger signal is received,

wherein the phase of the first clock signal at the time the trigger signal is received is indicative of a phase difference between first clock signal and a second clock signal that is used by the first device.

12. The apparatus of claim 11, wherein the first time value is loaded into the timer in a cycle of the first clock signal that terminates at the first-occurring edge in the first clock signal.

13. The apparatus of claim 11, further comprising:

a counter adapted to count of an oversampling clock for the duration of each cycle of the first clock signal, wherein the oversampling clock has a frequency that is greater than the frequency of the first clock signal, and

wherein the second device is configured to;

identify the phase of the first clock signal at the time the trigger signal is received by providing the first device with a number representing a number of periods of the oversampling clock counted from beginning of a clock cycle of the first clock signal until the trigger signal is received.

14. The apparatus of claim 11, wherein the trigger signal is received before arrival of the future point in time.

15. The apparatus of claim 11, wherein the trigger signal is received while the second device is exiting a low-power mode of operation when the data communication link is inactive.

16. The apparatus of claim 11, wherein the first device comprises a system timer incremented by the second clock signal.

17. The apparatus of claim 11, wherein the second clock signal has a frequency that is half the frequency of the first clock signal.

18. The apparatus of claim 17, wherein the phase of the first clock signal at the time the trigger signal is received indicates a difference between system time and a local time maintained by the timer of the second device.

19. The apparatus of claim 11, wherein the second device comprises a metastability-hardened flip-flop configured to receive the trigger signal from the data communication link.

20. A method for synchronizing system time used by devices coupled to a data communication link, comprising:

determining a first time value that corresponds to a future point in system time at a first device;

transmitting a second time value from the first device to a second device through the data communication link, the second time value being incrementally greater than the first time value;

transmitting a trigger signal from the first device to the second device through the data communication link when the first time value is determined to match a value output by a system timer operated by the first device, wherein the system timer is clocked using a first clock signal;

receiving from the second device an indication of phase of a second clock signal when the trigger signal was received by the second device, wherein the second clock signal is used by the second device to maintain a local timer; and

calculating a phase difference between the first clock signal and the second clock signal using the indication of the phase of the second clock signal when the trigger signal was received by the second device.

21. The method of claim 20, wherein the indication of phase is expressed as a number of periods of a third clock signal that is used by the second device, wherein the third clock signal has a frequency that is a multiple of the frequency of the first clock signal.

22. The method of claim 20, comprising:

entering a low-power mode of operation after transmitting the second time value to the second device; and

transmitting the trigger signal to the second device while exiting the low-power mode of operation,

wherein the data communication link is inactive during the low-power mode of operation.

23. The method of claim 20, wherein the first clock signal has a lower frequency than the second clock signal.

24. The method of claim 23, wherein the phase of the second clock signal at the time the trigger signal was received by the second device indicates a difference between system time maintained by the system timer and local time maintained by the local timer.

25. The method of claim 20, wherein the first device comprises a modem and the second device comprises a radio frequency integrated circuit.

26. An apparatus, comprising:

means for determining a first time value that corresponds to a future point in system time at a first device coupled to a data communication link;

means for transmitting a second time value from the first device to a second device through the data communication link, the second time value being incrementally greater than the first time value;

means for transmitting a trigger signal from the first device to the second device through the data communication link when the first time value is determined to match a value output by a system timer operated by the first device, wherein the system timer is clocked using a first clock signal;

means for receiving from the second device an indication of phase of a second clock signal when the trigger signal was received by the second device, wherein the second clock signal is used by the second device to maintain a local timer; and

means for calculating a phase difference between the first clock signal and the second clock signal using the indication of the phase of the second clock signal when the trigger signal was received by the second device.

27. The apparatus of claim 26, wherein the indication of phase is expressed as a number of periods of a third clock signal that is used by the second device, wherein the third clock signal has a frequency that is a multiple of the frequency of the first clock signal.

28. The apparatus of claim 26, wherein the means for transmitting the trigger signal is configured to:

transmit the trigger signal to the second device while the data communication link is exiting a low-power mode of operation,

wherein the data communication link enters the low-power mode of operation after the second time value is transmitted to the second device.

29. The apparatus of claim 26, wherein the first clock signal has a lower frequency than the second clock signal.

30. The apparatus of claim 29, wherein the phase of the second clock signal at the time the trigger signal was received by the second device indicates a difference between system time maintained by the system timer and local time maintained by the local timer.