Fusion bonded liquid crystal polymer circuit structure

• US 10,159,154 B2
• Filed: 09/24/2015
• Issued: 12/18/2018
• Est. Priority Date: 06/03/2010
• Status: Active Grant

• Current Assignee: LCP Medical Technologies Incorporated
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Vo, Peter DungBa
• Assistant Examiner(s): PARVEZ, AZM A
• Application Number:
  US14/864,215
• Publication Number:
  US 20160014908A1
• Time in Patent Office: 1,181 Days
• Field of Search: 830830, 830829, 830832, 830825, 8305921, 29830, 29829, 29832, 29825, 295921
• CPC Class Codes: B23K 2103/12 Copper or alloys thereof
• CPC Class Codes: B23K 2103/30 Organic material
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/1689 After-treatment
• CPC Class Codes: C23C 18/38 Coating with copper
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 2201/0141 Liquid crystal polymer [LCP]
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 3/421 Blind plated via connections H05K3/422, H05K3/423 and H05K3/425 take precedence
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: H05K 3/4635 laminating flexible circuit boards using additional insulating adhesive materials between the boards
• CPC Class Codes: H05K 3/4679 Aligning added circuit layers or via connections relative to previous circuit layers
• CPC Class Codes: Y10T 29/49002 : Electrical device making

Abstract

A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures. The stack is then fusion bonded to mechanically couple the first conductive pillars to the second conductive structures.

Claims

1. A method of making, a multilayered, fusion bonded circuit structure comprising the steps of:

attaching a first circuitry layer to a first major surface of a first liquid crystal polymer (LCP) substrate;

forming a plurality of first vias extending from a second major surface of the first substrate to the first circuitry layer;

plating the first vias;

applying a photo sensitive material to the first circuitry laver;

imaging the photo sensitive material to create a plurality of first recesses that expose locations on the first circuitry layer;

plating the first recesses to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses, the first conductive pillars extending above the first major surface of the first substrate;

forming a plurality of second recesses in a second LCP substrate corresponding to the plurality of the first conductive pillars;

plating the second recesses to form a plurality of second conductive structures that, extend between first and second major surfaces of the second substrate;

aligning the first conductive pillars with the second conductive structures;

positioning distal ends of the first conductive pillars at least partially in the second recesses of the second substrate before the fusion bonding step; and

fusion bonding the first and second LCP substrates to mechanically and electrically couple the first conductive pillars to the second conductive structures.

2. The method of claim 1 comprising the step of laser drilling the first and second recesses.

3. The method of claim 1 wherein the step of attaching the first circuitry layer to the first major surface of the first LCP substrate comprises the steps of:

plating the first major surface of the first LCP substrate with a seed layer of a conductive material;

applying a photo sensitive material to the seed layer of conductive material; and

forming the plurality of first recesses in the photo sensitive material.

4. The method of claim 3 comprising the steps of:

bulk plating the first recesses with a conductive material;

removing the photo sensitive material to reveal substantially rectangular conductive traces; and

etching the first LCP substrate to remove exposed portions of the seed layer adjacent the conductive traces.

5. The method of claim 1 comprising the step of fusion bonding an LCP material to the first major surface of the first LCP substrate to substantially surround the first circuit layer.

6. The method of claim 1 comprising the step of planarizing the major surfaces of the first and second substrates before the step of fusion bonding.

7. The method of claim 1 comprising the step of plating the second recesses to, form a plurality of second conductive pillars of solid metal.

8. The method of claim 1 wherein the second conductive structures comprise barrel plated vias, the method comprising the steps of plating the barrel plated vias to form a plurality of second conductive pillars of solid metal bonded to the first conductive pillars.

9. The method of claim 1 comprising locating the first conductive pillars on a pitch of less than 150 micrometers.

10. The method of claim 1 wherein the first conductive pillars have a height measured between the first and second major surfaces of less than about 150 micrometers.

11. The method of claim 1 comprising the step of attaching a second circuitry layer to a first major surface of the second substrate.

12. The method of claim 11 comprising the steps of:

bonding a third layer of LCP to an exposed surface of the second circuitry layer; and

laser drilling a plurality of vias from an exposed first major surface of the third layer to the second circuitry layer.

13. The method of claim 1 comprising the step of configuring the first conductive pillars to extend above the first major surface of the first substrate.

14. The method of claim 1 comprising the step of plating the second conductive structures after the fusion bonding step to form a plurality of second conductive pillars of solid metal bonded to the first conductive pillars.

15. The method of claim 1 comprising the steps of:

forming a plurality of through holes corresponding to the first conductive pillars and the second conductive structures in a bond layer of low melt LCP;

positioning the bond layer between the first and second substrates with the through holes aligned with the first conductive pillars and the second conductive structures before the fusion bonding step; and

fusion bonding the bond layer to the first and second substrates.

16. The method of claim 1 comprising the steps of:

preparing surfaces of one or more of the first or second recesses to receive electro-less plating; and

electro-less plating one or more of the first or second recesses before the plating step.

17. The method of claim 1 comprising the step of electrically coupling an IC device to a plurality of the second conductive structures along the first major surface of the second substrate.

18. A method of making a multilayered, fusion bonded circuit structure comprising the steps of:

attaching a first circuitry layer to a first major surface of a first liquid crystal polymer (LCP) substrate;

forming a plurality of first vias extending from a second major surface of the first substrate to the first circuitry layer;

plating the first vias;

applying a photo sensitive material to the first circuitry layer;

imaging the photo sensitive material to create a plurality of first recesses that expose locations on the first circuitry layer;

plating the first recesses to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses, the first conductive pillars extending above the first major surface of the first substrate;

forming a plurality of second recesses in a second LCP substrate corresponding to the plurality of the first conductive pillars;

plating the second recesses to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate;

forming a plurality of through holes corresponding to the first conductive pillars and the second conductive structures in a bond layer of low melt LCP;

positioning the bond layer between the first and second substrates with the through holes aligned with the first conductive, pillars and the second conductive structures, before the fusion bonding step; and

fusion bonding the bond layer to the first and second substrates.