System and method for forming a buried lower electrode in conjunction with an encapsulated MEMS device

• US 10,160,632 B2
• Filed: 08/17/2013
• Issued: 12/25/2018
• Est. Priority Date: 08/21/2012
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Graham, Andrew, Feyh, Ando, O'Brien, Gary
• Primary Examiner(s): Purvis, Sue A
• Assistant Examiner(s): Chi, Suberr
• Application Number:
  US13/969,522
• Publication Number:
  US 20140054730A1
• Time in Patent Office: 1,956 Days
• Field of Search: 257415-419
• CPC Class Codes: B81B 2207/092 Buried interconnects in the substrate or in the lid
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00015 for manufacturing microsystems

Abstract

A system and method for forming a sensor device with a buried first electrode includes providing a first silicon portion with an electrode layer and a second silicon portion with a device layer. The first silicon portion and the second silicon portion are adjoined along a common oxide layer formed on the electrode layer of the first silicon portion and the device layer of the second silicon portion. The resulting multi-silicon stack includes a buried lower electrode that is further defined by a buried oxide layer, a highly-doped ion implanted region, or a combination thereof. The multi-silicon stack has a plurality of silicon layers and silicon dioxide layers with electrically isolated regions in each layer allowing for both the lower electrode and an upper electrode. The multi-silicon stack further includes a spacer that enables the lower electrode to be accessible from a topside of the sensor device.

Claims

1. A method of forming a MEMS device comprising:

defining a first electrode in a silicon portion of a first wafer;

positioning a second wafer on an upper surface of the first wafer;

forming a second electrode in a first layer of the second wafer, the first layer located above the upper surface of the first wafer;

forming a third electrode in a second layer of the second wafer, the second layer located above an upper surface of the first layer;

forming a first contact in electrical communication with the first electrode, the first contact extending through the second layer and the first layer;

forming a second contact in electrical communication with the second electrode, the second contact extending through the second layer and electrically isolated from the first contact within the second layer; and

defining a third contact in electrical communication with the third electrode, the third contact accessible from above the second layer.

2. The method of claim 1, wherein the second wafer is an SOI wafer, the method further comprising:

providing a first portion of a first oxide layer over the first electrode;

providing a second portion of the first oxide layer over the first layer; and

connecting the first wafer and the second wafer at the respective first and second portions of the first oxide layer to electrically isolate the first electrode and the second electrode.

3. The method of claim 1, wherein the first wafer is an SOI wafer, the method further comprising:

doping a first region of the silicon portion with a first dopant type to form a first doped region, the first doped region defining the first electrode.

4. The method of claim 1, wherein the first electrode is defined in a silicon layer of a silicon wafer that is not an SOI wafer, the method further comprising:

doping a first region of the silicon layer with a first dopant type to form a first doped region; and

doping a second region of the silicon layer with a second dopant type to form a second doped region, wherein the first doped region is a N+ type doped region, the second doped region is a P+ type doped region, and the first doped region and the second doped region define the first electrode.

5. The method of claim 1, wherein the first electrode is defined in a silicon layer of a silicon wafer that is not an SOI wafer, the method further comprising:

doping a first region of the silicon layer with a first dopant type to form a first doped region;

doping a second region of the silicon layer with a second dopant type to form a second doped region; and

doping a third region of the silicon layer with a third dopant type to form a third doped region, the third doped region positioned between the first doped region and the second doped region, the first doped region being a P+ type doped region, the second doped region being a P type doped region, and the third doped region being a N−

well type doped region, wherein the first doped region and the third doped region define the first electrode.

6. The method of claim 1, wherein the first wafer includes a buried oxide layer, the method further comprising:

providing a first oxide layer on an upper surface of the first electrode;

forming a functional device within the first layer;

providing a second oxide layer on an upper surface of the first layer;

patterning a first portion of the first oxide layer and the second oxide layer to form a first portion of the first contact;

patterning a second portion of the first oxide layer and the second oxide layer and a portion of the buried oxide layer to form a first portion of a fourth contact, the fourth contact in electrical communication with a substrate layer located below the buried oxide layer;

etching first trenches in the first layer and the first oxide layer; and

filling the etched first trenches with a dielectric material to electrically isolate the first portion of the first contact and the first portion of the fourth contact within the first layer.

7. The method of claim 6, further comprising:

etching second trenches in the first layer within the first portion of the first contact and within the first portion of the fourth contact;

forming a first epitaxial portion of the second layer on the second oxide layer and within the second trenches;

etching third trenches through the first epitaxial portion of the second layer to form a second portion of the first contact, a second portion of the fourth contact, and a first portion of the second contact; and

filling the etched third trenches with the dielectric material to electrical isolate the second portion of the first contact, the second portion of the fourth contact, and the first portion of the second contact within the second layer.

8. The method of claim 7, further comprising:

forming a second epitaxial portion of the second layer on the first epitaxial portion;

releasing the functional device through vent holes formed in the second epitaxial portion and the first epitaxial portion; and

forming a third epitaxial portion of the second layer on the second epitaxial portion.

9. The method of claim 8, further comprising:

etching fourth trenches in the third epitaxial portion and the second epitaxial portion and stopping at selected ones of the etched and filled third trenches, the etched fourth trenches forming a third portion of the first contact, a third portion of the fourth contact, a second portion of the second contact, and a first portion of the third contact; and

filling the etched fourth trenches with the dielectric material to electrically isolate the third portion of the first contact, the third portion of the fourth contact, the second portion of the second contact, and the first portion of the third contact within the second layer.

10. The method of claim 9, further comprising:

forming a passive layer on the third epitaxial portion of the second layer;

patterning portions of the passive layer to expose portions of the third epitaxial portion corresponding to the third portion of the first contact, the third portion of the fourth contact, the second portion of the second contact, and the first portion of the third contact;

forming a metal layer on the patterned passive layer; and

patterning the metal layer to electrically isolate the first contact, the second contact, the third contact, and the fourth contact above the second layer.

11. The method of claim 8, wherein the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are deposited by an epitaxial deposition process.

12. The method of claim 6, wherein the dielectric material includes at least one of silicon dioxide, silicon nitride, and ALD alumina.

17. The method of claim 1, wherein:

the second electrode is formed so as to be positioned at least partially directly above the first electrode; and

the third electrode is formed so as to be positioned at least partially directly above the second electrode.

13. A MEMS device, comprising:

a first electrode in a silicon portion of a first wafer;

a second electrode in a first layer of a second wafer attached to the first wafer and located above an upper surface of the first wafer;

a third electrode in a second layer of the second wafer and located above an upper surface of the first layer;

a first contact in electrical communication with the first electrode, the first contact extending through the second layer and the first layer;

a second contact in electrical communication with the second electrode, the second contact extending through the second layer and electrically isolated from the first contact within the second layer; and

a third contact in electrical communication with the third electrode, the third contact accessible from above the second layer.

14. The device of claim 13, wherein the first electrode is defined in a first doped region of the first wafer, the first doped region including a first dopant type.

15. The device of claim 13, wherein the first electrode is defined in a silicon layer of a silicon wafer that is not an SOI wafer, the silicon layer including:

a doped first region of a first dopant type; and

a doped second region of a second dopant type, the first doped region being a N+ type doped region and the second doped region being a P+ type doped region, the first doped region and the second doped region defining the first electrode.

16. The device of claim 13, wherein the first electrode is defined in a silicon layer of a silicon wafer that is not an SOI wafer, the silicon layer including:

a doped first region of a first dopant type;

a doped second region of a second dopant type; and

a doped third region of a third dopant type, the third doped region positioned between the first doped region and the second doped region, the first doped region being a P+ type doped region, the second doped region being a P type doped region, and the third doped region being a N−

well type doped region, wherein the first doped region and the third doped region define the first electrode.

18. The device of claim 13, wherein:

the second electrode is positioned at least partially directly above the first electrode; and

the third electrode is positioned at least partially directly above the second electrode.