Wafer level packaging of infrared camera detectors

• US 10,161,803 B2
• Filed: 12/05/2016
• Issued: 12/25/2018
• Est. Priority Date: 07/27/2010
• Status: Active Grant

• Current Assignee: Teledyne FLIR LLC (Teledyne Technologies Incorporated)
• Original Assignee: FLIR Systems, Inc. (Teledyne Technologies Incorporated)
• Inventors: Carlson, Gregory A., Matson, Alex, Sharpe, Andrew, Beard, Davey, Schweikert, Paul, Simes, Robert
• Primary Examiner(s): Le, Peter D
• Application Number:
  US15/369,702
• Publication Number:
  US 20170328779A1
• Time in Patent Office: 750 Days
• Field of Search: None
• CPC Class Codes: G01J 1/0204 Compact construction
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: G01J 2005/0077 Imaging
• CPC Class Codes: G01J 2005/204 prepared by semiconductor processing, e.g. VLSI
• CPC Class Codes: G01J 5/02 Constructional details
• CPC Class Codes: G01J 5/0215 Compact construction
• CPC Class Codes: G01J 5/023 Particular leg structure or construction or shape; Nanotubes
• CPC Class Codes: G01J 5/046 Materials; Selection of thermal materials
• CPC Class Codes: G01J 5/10 using electric radiation detectors
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14669 Infrared imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H04N 23/23 : from thermal infrared radiation
• CPC Class Codes: H04N 23/52 : Elements optimising image sensor operation, e.g. for electromagnetic interference [EMI] protection or temperature control by heat transfer or cooling elements
• CPC Class Codes: H04N 5/33 : Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20
• CPC Class Codes: H10N 15/10 : Thermoelectric devices using thermal change of the dielectric constant, e.g. working above and below the Curie point
• CPC Class Codes: Y10T 29/49826 : Assembling or joining

Abstract

An infrared detector useful in, e.g., infrared cameras, includes a substrate having an array of infrared detectors and a readout integrated circuit interconnected with the array disposed on an upper surface thereof, for one or more embodiments. A generally planar window is spaced above the array, the window being substantially transparent to infrared light. A mesa is bonded to the window. The mesa has closed marginal side walls disposed between an outer periphery of a lower surface of the window and an outer periphery of the upper surface of the substrate and defines a closed cavity between the window and the array that encloses the array. A solder seal bonds the mesa to the substrate so as to seal the cavity.

Claims

1. An infrared detector, comprising:

a first substrate having an array of infrared detectors and a readout integrated circuit interconnected with the array disposed on an upper surface thereof;

a second substrate having side walls and a generally planar window spaced above the array, the window being substantially transparent to infrared light,

wherein the side walls are disposed on an upper surface of the first substrate and define a closed cavity between the first and second substrates that enclose the array;

a solder seal bonding a perimeter of the side walls of the second substrate to the first substrate so as to seal the cavity; and

at least one solder capture ring fully disposed around and/or within a perimeter of the solder seal and disposed on the first substrate adjacent to the side walls.

2. The infrared detector of claim 1, further comprising a plurality of solder capture rings, wherein at least one of the solder capture rings is fully disposed around an outer perimeter of the solder seal and at least one solder capture ring is fully disposed around an inner perimeter of the solder seal.

3. The infrared detector of claim 1, wherein the at least one solder capture ring is fully disposed around an outer perimeter of the solder seal.

4. The infrared detector of claim 1, wherein the at least one solder capture ring is fully disposed around an inner perimeter of the solder seal.

5. The infrared detector of claim 1, wherein the solder seal is connected to the at least one solder capture ring via one or more tabs.

6. The infrared detector of claim 1, wherein the array of infrared detectors comprise an array of microbolometers;

wherein at least one of the first substrate and the second substrate comprises silicon; and

further comprising at least one anti-reflective coating disposed on an upper and/or a lower surface of the window.

7. The infrared detector of claim 1, further comprising at least one electrical test pad disposed on the upper surface of the second substrate adjacent to an outer periphery of the window and coupled to the readout integrated circuit.

8. The infrared detector of claim 1, wherein the cavity and a lower surface of the window is formed using a Deep Reactive Ion Etching (DRIE) process.

9. The infrared detector of claim 1, wherein the solder seal comprises an alloy of titanium, nickel, and/or gold-tin-gold.

10. The infrared detector of claim 1, wherein the second substrate comprises a low-oxygen silicon.

11. An infrared camera comprising the infrared detector of claim 1, wherein the infrared detector comprises one of a plurality of infrared detectors singulated from a bonded sandwich of the first substrate and the second substrate, and wherein the infrared detector is part of an infrared camera.

12. The infrared camera of claim 11, further comprising:

a housing; and

one or more lenses coupled to the housing and configured to allow electromagnetic radiation to pass through onto the infrared detector.

13. A method for making an infrared detector, the method comprising:

providing a window wafer comprised of a semiconductor;

forming an array of cavities in a surface of the window wafer, each cavity defining a window substantially transparent to infrared light and surrounded by side walls, adjacent rows and columns of the array being separated from each other by dicing lanes;

providing a detector wafer having an upper surface with an array of infrared detector arrays corresponding in size and location to be disposed within the array of cavities in the window wafer, and a corresponding array of readout integrated circuits respectively interconnected with associated ones of the infrared detector arrays disposed thereon, adjacent rows and columns of the infrared detector arrays being separated from each other by dicing lanes;

forming an array of solder seals on the upper surface of the detector wafer respectively corresponding in size and location to the side walls on the window wafer;

forming at least one solder capture ring on the detector wafer around and/or within a perimeter of each of the solder seals thereon;

aligning the window wafer over the detector wafer such that the cavities of the window wafer are respectively disposed over corresponding ones of the infrared detector arrays;

bonding lower surfaces of the side walls with the upper surface of the detector wafer such that each of the cavities is sealed and a plurality of infrared detectors is defined between the two wafers;

evacuating at least partially each of the cavities; and

fusing the solder seals with the corresponding side walls on the upper surface of the detector wafer.

14. The method of claim 13, further comprising forming a plurality of solder capture rings, wherein at least one of the solder capture rings is fully disposed around an outer perimeter of at least one of the solder seals and at least one of the solder capture rings is fully disposed around an inner perimeter of at least one of the solder seals.

15. The method of claim 13, wherein at least one of the solder capture ring is fully disposed around an outer perimeter of each of the solder seals.

16. The method of claim 13, wherein at least one of the solder capture ring is fully disposed around an inner perimeter of each of the solder seals.

17. The method of claim 13, wherein each of the solder seals is connected to at least one of the solder capture rings via one or more tabs.

18. The method of claim 13, wherein forming the array of cavities comprises etching each of the cavities using a Deep Reactive Ion Etching (DRIE) process.

19. The method of claim 13, wherein the array of solder seals are formed on the upper surface of the detector wafer utilizing photolithography techniques and further comprising:

forming an anti-reflective coating on at least one of an upper and a lower surface of each of the windows;

forming a getter on a lower surface of each of the windows;

firing the getters during the bonding of the wafers;

slicing through the dicing lanes of the detector wafer to singulate the plurality of infrared detectors and to expose test pads on the upper surface of the detector wafer; and

performing a wafer level test of at least some of the plurality of infrared detectors using the exposed test pads.

20. The method of claim 13, wherein the solder seal comprises an alloy of titanium, nickel, and/or gold-tin-gold, and wherein the window wafer comprises a low-oxygen silicon.