Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently
First Claim
1. An automated test equipment (ATE) apparatus comprising:
- a computer system comprising a system controller, wherein said system controller, using a network switch, is communicatively coupled to a site module board comprising a tester processor and a plurality of FPGAs, wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs);
the plurality of FPGA components are communicatively coupled to said tester processor via a bus on said site module board, wherein each of said plurality of FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing a DUT of a plurality of DUTs; and
a plurality of I/O ports, each for communicating with a respective DUT and each communicatively coupled to a respective FPGA of said plurality of FPGAs, andwherein said tester processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in a different manner, wherein said plurality of functional modes comprises a hardware accelerator pattern generator mode, wherein, in the hardware accelerator pattern generator mode;
said tester processor is configured to generate all commands for coordinating testing of a plurality of DUTs; and
said hardware accelerator circuits of said plurality of FPGA components perform a step selected from the group comprising;
generate test pattern data, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs.
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Accused Products
Abstract
Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.
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Citations
32 Claims
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1. An automated test equipment (ATE) apparatus comprising:
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a computer system comprising a system controller, wherein said system controller, using a network switch, is communicatively coupled to a site module board comprising a tester processor and a plurality of FPGAs, wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs); the plurality of FPGA components are communicatively coupled to said tester processor via a bus on said site module board, wherein each of said plurality of FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing a DUT of a plurality of DUTs; and a plurality of I/O ports, each for communicating with a respective DUT and each communicatively coupled to a respective FPGA of said plurality of FPGAs, and wherein said tester processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in a different manner, wherein said plurality of functional modes comprises a hardware accelerator pattern generator mode, wherein, in the hardware accelerator pattern generator mode;
said tester processor is configured to generate all commands for coordinating testing of a plurality of DUTs; and
said hardware accelerator circuits of said plurality of FPGA components perform a step selected from the group comprising;
generate test pattern data, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for testing using an automated test equipment (ATE) comprising:
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transmitting instructions from a system controller of a computer system to a tester processor, wherein said system controller, using a network switch, is communicatively coupled to a site module board comprising the tester processor and a plurality of FPGAs, wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs); generating commands and data transparently from said tester processor for testing of a plurality of DUTs using hardware accelerator circuits programmed within a plurality of FPGA components, wherein said plurality of FPGA components is communicatively coupled to said tester processor via a bus on said site module board and wherein each hardware accelerator circuit is operable to test a DUT of said plurality of DUTs; communicating with a respective DUT through an I/O port, wherein said I/O port is communicatively coupled to a respective FPGA of said plurality of FPGAs; and operating the tester processor in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in a different manner, wherein said plurality of functional modes comprises a hardware accelerator pattern generator mode, wherein the hardware accelerator pattern generator mode further comprises;
generating all commands for coordinating testing of a plurality of DUTs using said tester processor; and
using said hardware accelerator circuits to perform a step selected from the group comprising;
generating all test pattern data, writing said test pattern data and comparing the test pattern data read from said plurality of DUTs. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A tester comprising:
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a system controller for controlling a test program for testing a plurality of DUTs; a plurality of modules operable to interface with and test said plurality of DUTs, said plurality of modules coupled to said system controller via a first communication bus, wherein each module comprises a site module board, and wherein each site module board comprises; a tester processor coupled to communicate with said system controller to receive instructions and data therefrom in accordance with said test program; a plurality of programmable instantiated tester blocks coupled to said tester processor via a second bus on said site module board, each programmable instantiated tester block operable to generate test data for application to a respective DUT in a way transparent to said test processor, further operable to receive and compare test data generated by said respective DUT in a way transparent to said tester processor, and further yet operable to be programmed to communicate with said respective DUT in a communication protocol compatible with said respective DUT, wherein said programmable instantiated tester blocks are implemented within Field Programmable Gate Array (FPGA) devices; a local memory coupled to said plurality of programmable instantiated tester blocks for storing test data therein; and a plurality of IO ports for coupling said plurality of DUTs to said plurality of modules wherein each respective programmable instantiated tester block is operable to control at least one respective DUT of said plurality of DUTs; wherein each module of said plurality of modules is operable in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of programmable instantiated tester blocks in a different manner, wherein one of the functional modes is a hardware accelerator pattern generator mode, wherein in the hardware accelerator pattern generator mode;
said tester processor is configured to generate all commands for coordinating testing of a plurality of DUTs; and
said plurality of programmable instantiated tester blocks are operable to perform a step selected from the group comprising;
generate test pattern data, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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Specification