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Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently

  • US 10,162,007 B2
  • Filed: 02/21/2013
  • Issued: 12/25/2018
  • Est. Priority Date: 02/21/2013
  • Status: Active Grant
First Claim
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1. An automated test equipment (ATE) apparatus comprising:

  • a computer system comprising a system controller, wherein said system controller, using a network switch, is communicatively coupled to a site module board comprising a tester processor and a plurality of FPGAs, wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs);

    the plurality of FPGA components are communicatively coupled to said tester processor via a bus on said site module board, wherein each of said plurality of FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing a DUT of a plurality of DUTs; and

    a plurality of I/O ports, each for communicating with a respective DUT and each communicatively coupled to a respective FPGA of said plurality of FPGAs, andwherein said tester processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in a different manner, wherein said plurality of functional modes comprises a hardware accelerator pattern generator mode, wherein, in the hardware accelerator pattern generator mode;

    said tester processor is configured to generate all commands for coordinating testing of a plurality of DUTs; and

    said hardware accelerator circuits of said plurality of FPGA components perform a step selected from the group comprising;

    generate test pattern data, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs.

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