Cognitive energy saving method and apparatus

• US 10,162,403 B2
• Filed: 05/29/2014
• Issued: 12/25/2018
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: MaxLinear Communications, LLC (f/k/a Entropic Communications, LLC) (Maxlinear Incorporated)
• Original Assignee: Entropic Communications, LLC (SoftBank Group Corp.)
• Inventors: Petrovic, Branislav, Safdar, Abul Shams, Jogadhenu, Sagar
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Harrington, Cheri
• Application Number:
  US14/290,066
• Publication Number:
  US 20150293579A1
• Time in Patent Office: 1,671 Days
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3231 Monitoring the presence, absence or movement of users
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Systems and methods for reducing the amount of power consumed by an electronic or electrical device by using collected knowledge of the operation of the device to determine when to place the device in an ultra-low power consumption mode.

Claims

1. A system for communication, the system comprising:

a set-top-box comprising;

a power supply within the set-top-box;

a first timing module comprising a first switch and low power control circuit comprising a charge retaining device;

power mode memory; and

an integrated circuit in the set-top-box, the integrated circuit comprising a processor, said processor configured to collect, in the power mode memory, information regarding usage patterns of the set-top box,

wherein;

the charge retaining device and the power supply are connected in parallel to an external power source via the first switch;

the low power control circuit is operable to control the first switch to control when the set-top-box enters and exits an ultra-low power control (ULPC) mode, wherein the control of the first switch is based on the information regarding the usage patterns in the power mode memory; and

the low power control circuit recharges the charge retaining device using the external power source via said first switch;

a standby processor in an always-on power island, the standby processor coupled to the processor, which is powered down when the set-top-box enters said UPLC mode and is powered up when the set-top-box exits the ULPC mode, the standby processor coupled to a plurality of interface modules that are integrated into different power islands and operable to receive inputs from a source external to the set-top-box during the ULPC mode; and

a second timing module independent of the first timing module and coupled to the processor and the standby processor, said second timing module for controlling the coupling of the power supply to the integrated circuit.

2. The system of claim 1, wherein the charge retaining device is configured to maintain sufficient power when the power supply is turned off to power functions of the low power control circuit.

3. The system of claim 2, wherein the first timing module is configured to generate the information regarding the usage patterns.

4. The system of claim 1, wherein the information regarding the usage patterns is generated in a head-end external to the set-top-box.

5. The system of claim 1, wherein the information regarding the usage patterns is generated in a gateway external to the set-top-box.

6. The system of claim 1, wherein the power supply has an enable input which allows the power supply to be turned off during operation in the ULPC mode.

7. The system of claim 1, wherein the charge retaining device is a capacitor.

8. The system of claim 1, wherein the charge retaining device is a battery.

9. The system of claim 1, wherein the low power control circuit is configured to provide a control signal to turn the power supply on to restore a charge in the charge retaining device before the charge in the charge retaining device drops to a level that is no longer sufficient to power the functions of the low power control circuit.

10. The system of claim 1, wherein:

the set-top-box comprises a second power supply; and

the low power control circuit is powered by the second power supply.

11. The system of claim 1, wherein:

the low power control circuit comprises a timer; and

the control of the first switch is based on a state of the timer.

12. The system of claim 1, wherein:

the set-top-box comprises a user-activated switch that is coupled to the low power control circuit, and that is configured to, when activated by a user, cause the low power control circuit to turn the power supply back on.

13. The system of claim 1, wherein:

the low power control circuit is configured to monitor a state of at least one environmental sensor; and

the control of the first switch is based on the state of the at least one environmental sensor.

14. The system of claim 1, wherein the control of the first switch is based upon probability of achieving particular predetermined power consumption goals.

15. The system of claim 3, wherein the first timing module is configured to record, in the power mode memory, failed attempts to turn the power supply on.

16. The system of claim 15, wherein the first timing module is configured to detect when the external power source has been reconnected to the set-top-box, and to turn the power supply on upon detecting that the external power source has been reconnected to the set-top-box.

17. A device comprising:

a power supply;

an integrated circuit comprising;

a power grid;

a power mode memory;

a processor configured to;

collect, in the power mode memory, information regarding usage patterns of the device; and

determine, from the usage patterns, when the integrated circuit is to enter an ultra-low power control (ULPC) mode;

a first always-on power island isolated from the power grid, the first always-on power island including a standby processor, the standby processor coupled to a plurality of interface modules that are integrated into different power islands and operable to receive inputs from a source external to the set-top-box during the ULPC mode; and

a first timing module residing on a second always-on power island isolated from the first always-on power island and the power grid, wherein;

the first timing module comprises a first switch that is configured to disconnect the power grid from the power supply when the integrated circuit enters the ULPC mode, and reconnect the power grid to the power supply when the integrated circuit exits the ULPC mode;

the first timing module is coupled to the processor;

the first timing module is configured to receive signals from the processor to enter the ULPC mode;

the first timing module comprises a first timer set by the processor to determine an amount of time the integrated circuit will remain in the ULPC mode;

the first timing module is coupled to the standby processor;

the first timing module is configured to receive a signal from the standby processor to exit the ULPC mode prior to the first timer timing out;

the first timing module comprises a first charge retaining device;

the processor is powered down by the first timing module when the integrated circuit enters the ULPC mode and is powered up when the integrated circuit exits the ULPC mode;

the first timing module is configured to receive power from the first charge retaining device during operation in the ULPC mode;

the first timing module recharges the charge retaining device using the power supply when the integrated circuit is in the ULPC mode; and

the first always-on power island is configured to receive power from the first charge retaining device during operation in the ULPC mode; and

a second timing module independent of the first timing module and coupled to the processor, said second timing module for controlling the coupling of an external power source to the power supply.

18. The device of claim 17, the second timing module comprising:

a second switch coupled to the power supply for turning the power supply on and off; and

a low power control circuit, the low power control circuit having a second timer and a second charge retaining device, the low power control circuit coupled to the processor and receiving from the processor a ULPC control signal, the low power control circuit coupled to the second switch and providing a switch control signal to the second switch to cause the second switch to turn the power supply off in response to the ULPC control signal, and providing the switch control signal to the second switch to turn the power supply on in response to the second timer;

wherein the processor determines when to send the ULPC control signal to the low power control circuit based on the information regarding usage patterns.

19. The device of claim 17, the first always-on power island further including a plurality of interface modules, each interface module monitoring one or more of environmental sensors, the interface module sending a signal to the standby processor when a state of one of the one or more environmental sensors changes, and the standby processor sending a signal to the first timing module to exit the ULPC mode when the state of the one of the one or more environmental sensors changes.