Ratiometric mutual-capacitance-to-code converter

• US 10,162,467 B2
• Filed: 06/16/2017
• Issued: 12/25/2018
• Est. Priority Date: 03/08/2017
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Maharyta, Andriy
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): Maini, Rahul
• Application Number:
  US15/625,339
• Publication Number:
  US 20180260076A1
• Time in Patent Office: 557 Days
• Field of Search: 324678
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/04182 Filtering of noise external to the device and not generated by digitiser components
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance sensing circuit also includes a comparator configured to generate an output based on comparing a first voltage of the first modulation capacitor with a second voltage of the second modulation capacitor, and initiate a transition between the first phase and the second phase in response to the comparing.

Claims

1. A capacitance sensing circuit, comprising:

a set of bridge switches coupled with a reference cell and a sensor cell, wherein the set of bridge switches is configured to;

over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and

over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell; and

a comparator configured to;

generate an output based on comparing a first voltage of the first modulation capacitor with a second voltage of the second modulation capacitor, and

initiate a transition between the first phase and the second phase in response to the comparing.

2. The capacitance sensing circuit of claim 1, wherein the set of bridge switches comprises a first switch coupling the reference cell with the second modulation capacitor, a second switch coupling the reference cell with the first modulation capacitor, a third switch coupling the sensor cell with the first modulation capacitor, and a fourth switch coupling the sensor cell with the second modulation capacitor.

3. The capacitance sensing circuit of claim 1, further comprising a transmit (TX) driver configured to supply a TX signal to each of the reference cell and the sensor cell.

4. The capacitance sensing circuit of claim 3, wherein the set of bridge switches is further configured to, during the second phase:

while an output voltage of the TX driver is higher than both of the first voltage and the second voltage, charge the first modulation capacitor by closing the third switch to connect the sensor cell to the first modulation capacitor while simultaneously charging the second modulation capacitor by closing the first switch to connect the reference cell to the second modulation capacitor; and

while the output voltage of the TX driver is lower than both of the first voltage and the second voltage, discharge the first modulation capacitor by closing the second switch to connect the reference cell to the first modulation capacitor while simultaneously discharging the second modulation capacitor by closing the fourth switch to connect the sensor cell to the second modulation capacitor.

5. The capacitance sensing circuit of claim 1, further comprising a transmit (TX) driver configured to supply a TX signal to the sensor cell, wherein the set of bridge switches is further configured to, during the first phase:

while an output voltage of the TX driver is higher than the first voltage, charge the first modulation capacitor by closing the third switch to connect the sensor cell to the first modulation capacitor; and

while the output voltage of the TX driver is lower than the second voltage, discharge the second modulation capacitor by closing the fourth switch to connect the sensor cell to the second modulation capacitor.

6. The capacitance sensing circuit of claim 1, wherein the capacitance of the reference cell is greater than the capacitance of the sensor cell.

7. The capacitance sensing circuit of claim 1, further comprising a sequencer configured to:

output a first sequence of switching signals for operating the set of bridge switches during the first phase;

transition between the first phase and the second phase in response to the comparing determining that the first voltage is greater than the second voltage;

output a second sequence of switching signals for operating the set of bridge switches during the second phase; and

transition between the second phase and the first phase in response to the comparing determining that the second voltage is greater than the first voltage.

8. The capacitance sensing circuit of claim 7, wherein the sequencer further comprises a break-before-make module configured to generate two pairs of complementary non-overlapping switching signals based on a modulation frequency.

9. The capacitance sensing circuit of claim 8, wherein the TX driver is configured to generate the TX signal by alternately switching a TX driver output between a first voltage and a second voltage at a clock frequency, and wherein the clock frequency is lower than the modulation frequency.

10. The capacitance sensing circuit of claim 1, further comprising a flip-flop configured to generate an output bitstream based on the output of the comparator, wherein an average duty cycle of the output bitstream is substantially proportional to the capacitance of the sensor cell.

11. The capacitance sensing circuit of claim 1, further comprising a fully differential integrator circuit, wherein the first modulation capacitor is connected to a positive input and a negative output of a differential amplifier of the integrator circuit, and the second modulation capacitor is connected between a negative input and a positive output of the differential amplifier.

12. A capacitance sensing method, comprising:

over a first phase, increasing a voltage difference between a first voltage of a first modulation capacitor and a second voltage of a second modulation capacitor;

over a second phase, decreasing the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell;

comparing the first voltage with the second voltage; and

in response to the comparing, transitioning between the first phase and the second phase.

13. The capacitance sensing method of claim 12, further comprising, during the second phase:

supplying a TX signal to each of the reference cell and the sensor cell,

while a voltage of the TX signal is higher than both of the first voltage and the second voltage, charging the first modulation capacitor by closing the third switch to connect the sensor cell to the first modulation capacitor while simultaneously charging the second modulation capacitor by closing the first switch to connect the reference cell to the second modulation capacitor,

while the voltage of the TX signal is lower than both of the first voltage and the second voltage, discharging the first modulation capacitor by closing the second switch to connect the reference cell to the first modulation capacitor while simultaneously discharging the second modulation capacitor by closing the fourth switch to connect the sensor cell to the second modulation capacitor.

14. The capacitance sensing method of claim 12, further comprising, during the first phase:

supplying a TX signal to the sensor cell;

while a voltage of the TX signal is higher than the first voltage, charging the first modulation capacitor by closing the third switch to connect the sensor cell to the first modulation capacitor; and

while the voltage of the TX signal is lower than the second voltage, discharging the second modulation capacitor by closing the fourth switch to connect the sensor cell to the second modulation capacitor.

15. The capacitance sensing method of claim 12, further comprising:

outputting a first sequence of switching signals for operating the set of bridge switches during the first phase;

transitioning between the first phase and the second phase in response to the comparing determining that the first voltage is greater than the second voltage;

outputting a second sequence of switching signals for operating the set of bridge switches during the second phase; and

transitioning between the second phase and the first phase in response to the comparing determining that the second voltage is greater than the first voltage.

16. The capacitance sensing method of claim 15, further comprising generating two pairs of complementary non-overlapping switching signals based on a modulation frequency.

17. The capacitance sensing method of claim 12, further comprising generating an output bitstream based on the output of the comparator, wherein an average duty cycle of the output bitstream is substantially proportional to the capacitance of the sensor cell.

18. A capacitance sensing system, comprising:

a capacitive sensor cell;

a reference cell;

a transmit (TX) driver configured to supply a TX signal to each of the reference cell and the capacitive sensor cell;

a first modulation capacitor;

a second modulation capacitor;

a set of bridge switches coupled with the reference cell and capacitive sensor cell and configured to;

over a first phase, increase a voltage difference between a first voltage of the first modulation capacitor and a second voltage of the second modulation capacitor, and

over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the capacitive sensor cell and a capacitance of the reference cell; and

a comparator configured to;

generate an output based on comparing the first voltage with the second voltage, and

initiate a transition between the first phase and the second phase in response to the comparing.

19. The capacitance sensing system of claim 18, wherein a capacitance of the first modulation capacitor and a capacitance of the second modulation capacitor are each greater than 100 times a sum of the capacitance of the reference cell and a parasitic capacitance of the reference cell, and wherein the capacitance of the reference cell is greater than the capacitance of the capacitive sensor cell.

20. The capacitance sensing system of claim 18, wherein the capacitive sensor cell comprises a pair of sensor electrodes, and wherein the capacitance of the capacitive sensor cell is a mutual capacitance between the pair of sensor electrodes, and wherein the output generated by the comparator indicates the mutual capacitance between the pair of sensor electrodes.

21. The capacitance sensing system of claim 18, further comprising a flip-flop configured to generate an output bitstream based on the output generated by the comparator, wherein the TX driver is configured to generate the TX signal by alternately switching a TX driver output between a source voltage and a ground voltage at a clock frequency, wherein a duty cycle of the output bitstream is substantially proportional to the capacitance of the sensor cell and is independent from the source voltage and the clock frequency.