Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

• US 10,162,533 B2
• Filed: 03/14/2017
• Issued: 12/25/2018
• Est. Priority Date: 09/25/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Camp, Charles J., Fisher, Timothy J., Fry, Aaron D., Ioannou, Nikolas, Koltsidas, Ioannis, Pletka, Roman, Tomic, Sasa
• Primary Examiner(s): Chan, Tracy C.
• Application Number:
  US15/458,883
• Publication Number:
  US 20170185298A1
• Time in Patent Office: 651 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A computer-implemented method, according to one embodiment, includes: maintaining, by a processor, a first open logical erase block for user writes; maintaining, by the processor, a second open logical erase block for relocate writes; receiving, by the processor, a first data stream having the user writes; transferring, by the processor, the first data stream to the first open logical erase block; receiving, by the processor, a second data stream having the relocate writes; and transferring, by the processor, the second data stream to the second open logical erase block. Moreover, the first and second open logical erase blocks are different logical erase blocks. Other systems, methods, and computer program products are described in additional embodiments.

Claims

1. A computer-implemented method, comprising:

maintaining, by a processor, a first open logical erase block for user writes;

maintaining, by the processor, a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks;

receiving, by the processor, a first data stream having the user writes;

transferring, by the processor, the first data stream to the first open logical erase block;

receiving, by the processor, a second data stream having the relocate writes;

transferring, by the processor, the second data stream to the second open logical erase block;

receiving a third data stream;

and mixing the third data stream with the first data stream, the second data stream and/or another data stream in response to determining that an open logical erase block is not available for assignment to the third data stream, wherein mixing the third data stream with the first data stream, the second data stream and/or another data stream is based on a comparison between information associated with the first data stream, the second data stream and/or another data stream, the information being selected from a group consisting of;

a speed of the data streams, a number of open logic erase blocks, a number and/or size of cache, and a temperature of data.

2. The computer-implemented method of claim 1, comprising:

assigning a first timeout value to the first open logical erase block; and

assigning a second timeout value to the second open logical erase block.

3. The computer-implemented method of claim 2, comprising:

reassigning at least one of the first and second open logical erase blocks to a different data stream in response to at least one of the first and second timeouts of the respective first and second open logical erase blocks-expiring.

4. The computer-implemented method of claim 2, wherein the first and second timeout values are determined based on a logical erase block write interval.

5. The computer-implemented method of claim 4, wherein the first and second timeout values are between about two and about five times a length of the logical erase block write interval.

6. The computer-implemented method of claim 1, comprising:

performing heat segregation on the data streams by assigning a third open logical erase block to a data stream having data hotter than data in another data stream.

7. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions readable and/or executable by a processor to cause the processor to perform a method comprising:

receiving, by the processor, a first data stream and a second data stream concurrently, wherein the first data stream includes user writes, wherein the second data stream includes relocate writes;

identifying, by the processor, a first open logical erase block;

transferring, by the processor, the first data stream having the user writes to the first open logical erase block;

terminating, by the processor, the transfer of the first data stream to the first open logical erase block;

causing, by the processor, transfer of the second data stream having the relocate writes either (a) to a second open logical erase block that is different than the first logical erase block, or (b) to the first open logical erase block after the transfer of the first data stream to the first open logical erase block is terminated and the first open logical erase block is reassigned to the second data stream;

assigning, by the processor, a first timeout value to the first open logical erase block;

assigning, by the processor, a second timeout value to the second open logical erase block, receiving, by the processor, a third data stream; and

mixing, by the processor, the third data stream with the first data stream, the second data is not available for assignment to the third data stream, wherein mixing the third data stream with the first data stream, the second data stream and/or another data stream is based on a comparison between information associated with the first data stream, the second data stream and/or another data stream, the information being selected from a group consisting of a speed of the data streams, a number of open logic erase blocks, a number and/or size of cache, and a temperature of data.

8. The computer program product of claim 7, wherein terminating the transfer of the first data stream to the first open logical erase block is performed upon filling a first cache.

9. The computer program product of claim 7, wherein the first and second timeout values are determined based on logical erase block write intervals.

10. The computer program product of claim 7, wherein the program instructions are readable and/or executable by the processor to cause the processor to perform the method comprising:

reassigning, by the processor, at least one of the first and second open logical erase block to a different data stream in response to at least one of the first and second timeouts of the respective first and second open logical erase blocks expiring.

11. The computer program product of claim 7, wherein the program instructions are readable and/or executable by the processor to cause the processor to perform the method comprising:

receiving, by the processor, a third data stream;

determining, by the processor, if the third data stream is substantially similar to the first data stream or the second data stream;

storing, by the processor, the third data stream in a same location as the first data stream in response to determining that the third data stream is substantially similar to the first data stream;

storing, by the processor, the third data stream in the same location as the second data stream in response to determining that the third data stream is substantially similar to the second data stream; and

buffering, by the processor, the third data stream in a second cache in response to determining that the third data stream is not substantially similar to the first data stream or the second data stream.

12. A system, comprising:

a processor and logic integrated with and/or executable by the processor, the logic being configured to;

maintain a first open logical erase block for user writes;

maintain a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks;

receive a first data stream having the user writes;

transfer an entirety of the first data stream to the first open logical erase block;

receive a second data stream having the relocate writes;

transfer an entirety of the second data stream to the second open logical erase block;

receive a third data stream; and

mix the third data stream with the first data stream, the second data stream and/or another data stream in response to determining that an open logical erase block is not available for assignment to the third data stream, wherein mixing the third data stream with the first data stream, the second data stream and/or another data stream is based on a comparison between information associated with the first data stream, the second data stream and/or another data stream, the information being selected from a group consisting of a speed of the data streams, a number of open logic erase blocks, a number and/or size of cache, and a temperature of data.

13. The system of claim 12, wherein the logic is further configured to:

assign a first timeout value to the first open logical erase block; and

assign a second timeout value to the second open logical erase block.

14. The system of claim 13, wherein the logic is further configured to:

reassign at least one of the first and second open logical erase blocks to a different data stream in response to at least one of the first and second timeouts of the respective first and second open logical erase blocks expiring,

wherein the first and second timeout values are determined based on a logical erase block write interval.

15. The system of claim 12, wherein the logic is further configured to:

perform heat segregation on the data streams by assigning a third open logical erase block to a data stream having data hotter than data in another data stream.

16. The system of claim 12, wherein the logic is further configured to:

receive a fourth data stream;

buffer the fourth data stream in a cache; and

mix the fourth data stream with one of the first, second and third data streams in response to determining that the cache has been filled to or past a certain capacity.