System and method for controlling a programmable deduplication ratio for a memory system

• US 10,162,554 B2
• Filed: 10/04/2016
• Issued: 12/25/2018
• Est. Priority Date: 08/03/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Zheng, Hongzhong, Malladi, Krishna, Niu, Dimin
• Primary Examiner(s): Huson, Zachary K
• Application Number:
  US15/285,437
• Publication Number:
  US 20180039443A1
• Time in Patent Office: 812 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0641 De-duplication techniques
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

A memory module has a logic including a programming register, a deduplication ratio control logic, and a deduplication engine. The programming register stores a maximum deduplication ratio of the memory module. The control logic is configured to control a deduplication ratio of the memory module according to the maximum deduplication ratio. The deduplication ratio is programmable by the host computer.

Claims

1. A memory module comprising:

a logic comprising a programming register, a deduplication ratio control logic, and a deduplication engine; and

a host interface to a host computer,

wherein the programming register stores a maximum deduplication ratio of the memory module,

wherein the control logic is configured to control a deduplication ratio of the memory module according to the maximum deduplication ratio, and

wherein the deduplication ratio is programmable by the host computer.

2. The memory module of claim 1, wherein the control logic is further configured to communicate the deduplication ratio of the memory module to the host computer via the host interface.

3. The memory module of claim 1, wherein the deduplication ratio of the memory module is programmed at production of the memory module.

4. The memory module of claim 1, wherein the deduplication ratio of the memory module is programmed at a system boot time.

5. The memory module of claim 1, further comprising a hash table memory, wherein the hash table memory comprises an address lookup table (LUT), a hash table, and a buffer memory.

6. The memory module of claim 5, wherein the deduplication ratio control logic is configured to control a table size of the address lookup table to limit a virtual capacity of the deduplication memory module according to the programmed deduplication ratio stored in the deduplication ratio register.

7. The memory module of claim 1, wherein the host interface is a double data rate (DDR) interface.

8. The memory module of claim 1, wherein the host interface is a peripheral component interconnect express (PCIe) interface.

9. A method comprising:

implementing a logic in a memory module, the logic comprising a programming register, a deduplication ratio control logic, and a deduplication engine;

storing a maximum deduplication ratio of the memory module in the programming register;

programming a deduplication ratio by the host computer; and

controlling the deduplication ratio of the memory module according to the maximum deduplication ratio.

10. The method of claim 9, further comprising communicating the deduplication ratio of the memory module to a host computer via a host interface.

11. The method of claim 9, wherein the deduplication ratio of the memory module is programmed at production of the memory module.

12. The method of claim 9, wherein the deduplication ratio of the memory module is programmed at a system boot time.

13. The method of claim 9, further comprising providing a hash table memory including an address lookup table (LUT), a hash table, and a buffer memory.

14. The method of claim 13, further comprising controlling a table size of the address lookup table to limit a virtual capacity of the deduplication memory module according to the programmed deduplication ratio stored in the deduplication ratio register.

15. The method of claim 11, wherein the host interface is a double data rate (DDR) interface.

16. The method of claim 11, wherein the host interface is a peripheral component interconnect express (PCIe) interface.