Multi-partitioning of memories

• US 10,162,556 B2
• Filed: 08/24/2017
• Issued: 12/25/2018
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Caraccio, Danilo, Confalonieri, Emanuele, Tiziani, Federico
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US15/685,926
• Publication Number:
  US 20170351458A1
• Time in Patent Office: 488 Days
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2213/3804 Memory card connected to a computer port directly or by means of a reader/writer
• CPC Class Codes: G06F 2213/3854 Control is performed at the peripheral side
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0637 Permissions
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Various embodiments comprise devices and methods to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the device is to manage logical memory partitioning on each of multiple memory devices that are based on differing, hybrid-memory technologies, the device is further to hide an actual storage media type of the multiple memory devices from the host through abstracted logical interface blocks. Additional devices and methods are described.

Claims

1. A memory device, comprising:

multiple memory devices based on differing, hybrid-memory technologies, the multiple memory devices including a first group of memory based on a first memory technology and a second group of memory based on a second memory technology;

an interface controller configured to be interposed between a memory controller unit host and the multiple memory devices, the interface controller to manage logical memory partitioning on each of the multiple memory devices, the interface controller being further configured to hide an actual storage media type of the multiple memory devices from the memory control unit host through abstracted logical interface blocks; and

a second interface controller coupled in series between the interface controller and the second group of memory.

2. The memory device of claim 1, wherein the multiple memory devices include a NAND Flash Memory coupled to the interface controller and a Phase-Change Memory (PCM) coupled to the interface controller, the interface controller to reconfigure partitions according to instructions received from the memory controller unit host.

3. The memory device of claim 2, wherein the NAND Flash Memory is a Multi-Level Cell (MLC) NAND Flash Memory device.

4. The memory device of claim 1, wherein the interface controller includes a register management block to track logical memory partitioning.

5. The memory device of claim 1, wherein the multiple memory devices include an embedded multi-media card (e-MMC).

6. The memory device of claim 1, wherein the interface controller is configured to inhibit selected actions during execution of commands received from the memory controller unit host.

7. The memory device of claim 1, wherein the interface controller is coupled to the first group of memory.

8. The memory device of claim 1, wherein the second interface controller is to manage commands transferred to the second group of memory only.

9. The memory device of claim 1, wherein during a power management mode, both the interface controller and the second interface controller are configured to execute state transitions to an inactive state and only the first interface controller replies is to reply to the memory controller unit host.

10. A method, comprising:

managing commands through a first interface controller to a first group of memory devices, the first interface controller interposed between a memory controller unit host and the first group of memory devices, the interface controller to manage logical memory partitioning on each of the first group of memory devices;

managing commands through a second interface controller to a second group of memory devices, the first group of memory devices and the second group of memory devices being based on differing, hybrid-memory technologies, the second interface controller coupled in series between the first interface controller and the second group of memory devices; and

hiding an actual storage media type of the groups of memory devices from the memory control unit host through abstracted logical interface blocks.

11. The method of claim 10, further comprising configuring the first type of non-volatile memory to not have an attribute enhanced set.

12. The method of claim 11, further comprising, based on a request from a host, configuring at least portions of the first group of memory devices to include the attribute enhanced set.

13. The method of claim 10, further comprising configuring the second group of memory devices to have an attribute enhanced set.

14. The method of claim 10, further comprising executing state transitions to reach an inactive state during a power management mode in at least one of the interface controllers.

15. A memory device, comprising:

multiple memory devices based on differing, hybrid-memory technologies;

a first interface controller interposed between a memory controller unit host and a first group of the multiple memory devices, the first interface controller to manage logical memory partitioning on each of the first group of memory devices; and

a second interface controller coupled in series between the first interface controller and a second group of the multiple memory devices, the second interface controller to manage commands to the second group of memory devices only, at least one of the first interface and the second interface to hide an actual storage media type of the groups of memory devices from the memory control unit host through abstracted logical interface blocks.

16. The memory device of claim 15, wherein the first interface controller is configured to be aware of the second interface controller and the second interface controller is configured not to be aware of the first interface controller.

17. The memory device of claim 15, further comprising a register to inhibit a response in the second interface controller while the first interface controller is configured to generate the response to the host.