Method and system for assigning a computational block of a software program to cores of a multi-processor system

• US 10,162,679 B2
• Filed: 04/01/2016
• Issued: 12/25/2018
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Levin, Mikhail Petrovich, Slesarenko, Alexander Vladimirovich, Zhang, Hongbo
• Primary Examiner(s): Ghaffari, Abu
• Application Number:
  US15/088,974
• Publication Number:
  US 20160239348A1
• Time in Patent Office: 998 Days
• Field of Search: None
• CPC Class Codes: G06F 2209/5017 Task decomposition
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for assigning a computational block of a software program to cores of a multi-processor system includes: evaluating a first number of available cores of a first type of the multi-processor system and a second number of available cores of a second type of the multi-processor system; determining a first number of loops of the computational block for binding with the cores of the first type and a second number of loops of the computational block for binding with the cores of the second type; binding the first number of loops with the cores of the first type and binding the second number of loops with the cores of the second type; and executing the loops of the computational block according to the binding.

Claims

1. A method for dynamic mapping of a computational block of a software program to cores of a multi-processor system at run-time, the method comprising:

evaluating, by the multi-processor system, a first number, K_1act, of available cores of a first type of the multi-processor system and a second number, K_2act, of available cores of a second type of the multi-processor system, wherein evaluating the first number, K_1act, of available cores is based on evaluating a number of cores of the first type busy with a background load of the multi-processor system, and wherein evaluating the second number, K_2act, of available cores is based on evaluating a number of cores of the second type busy with the background load of the multi-processor system;

determining, by the multi-processor system, a first number, n1, of loops of the computational block for binding with the available cores of the first type and a second number, n2, of loops of the computational block for binding with the available cores of the second type, wherein the computational block includes a plurality of loops, wherein the first number, n1, of loops is determined based on the first number of available cores of the first type, K_1act, the second number of available cores of the second type, K_2act, a clock frequency of a core of the first type, a clock frequency of a core of the second type, and a total number, N, of loops of the computational block, and according to the following relation;

2. The method of claim 1, wherein determining the first number, n1, and the second number, n2, of loops is according to a load balancing relation with respect to the available cores of the first type and the available cores of the second type.

3. The method of claim 1, wherein determining the first number, n1, and second number, n2, of loops is in accordance with a performance of the cores of the first type and a performance of the cores of the second type, respectively.

4. The method of claim 1, wherein the first number, n1, of loops is further determined based on at least one of the following parameters:

a loop execution time, T1, on a first core, and a loop execution time, T2, on a second core.

5. The method of claim 1, wherein a sum of the first number, K_1act, of available cores of the first type and the number of cores of the first type busy with the background load of the multi-processor system corresponds to the total number, K1, of cores of the first type;

and

wherein a sum of the second number, K_2act, of available cores of the second type and the number of cores of the second type busy with the background load of the multi-processor system corresponds to the total number, K2, of cores of the second type.

6. The method of claim 1, wherein the multi-processor system comprises a multi-core and many-core heterogeneous computing system.

7. The method of claim 1, wherein the computational block of the software program comprises a massive parallel computational block.

8. The method of claim 1, wherein a power consumption of a core of the first type is different from a power consumption of a core of the second type.

9. A non-transitory computer-readable medium storing instructions that, when executed, cause a computer to perform dynamic mapping of a computational block of a software program to cores of a multi-processor system that includes cores of a first type and cores of a second type, by performing the steps of:

evaluating a first number, K_1act, of available cores of a first type of the multi-processor system and a second number, K_2act, of available cores of a second type of the multi-processor system, wherein evaluating the first number, K_1act, of available cores is based on evaluating a number of cores of the first type busy with a background load of the multi-processor system, and wherein the evaluating the second number, K_2act, of available cores is based on evaluating a number of cores of the second type busy with the background load of the multi-processor system;

determining a first number, n1, of loops of the computational block for binding with the cores of the first type and a second number, n2, of loops of the computational block for binding with the cores of the second type, wherein the first number, n1, of loops is determined based on the first number of available cores of the first type, K_1act, the second number of available cores of the second type, K_2act, a clock frequency of a core of the first type, a clock frequency of a core of the second type, and a total number, N, of loops of the computational block, and according to the following relation;