Method and system for high precision time synchronization

• US 10,162,792 B2
• Filed: 10/13/2016
• Issued: 12/25/2018
• Est. Priority Date: 10/13/2016
• Status: Active Grant

• Current Assignee: Baidu USA LLC (Baidu Incorporated)
• Original Assignee: Baidu USA LLC (Baidu Incorporated)
• Inventors: Shao, Wesley, Surabhi, Vivek
• Primary Examiner(s): Martinez, David E
• Application Number:
  US15/292,921
• Publication Number:
  US 20180107626A1
• Time in Patent Office: 803 Days
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 9/4406 Loading of operating system

Abstract

In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock.

Claims

1. A data processing system, comprising:

a processor;

a Peripheral Component Interface Express (PCIe) link; and

a time processing device coupled to the processor via the PCIe link, the time processing device including time processing logic and a time register, wherein the time processing logic is to receive time data representing date and time from a time data source, and store the time data in the time register,

wherein the time processing device comprises

a first input to receive a first signal from the time data source, the first signal indicating that an update of the time data is available from the time data source, and

a second input to receive a message having the updated time data from the time data source,

wherein the time processing logic is to

detect the first signal received from the first input,

in response to the first signal, decode the time data received from the second input, and

store the decoded time data in the time register, and

wherein the processor retrieves the time data from the time register via a single read instruction over the PCIe link and updates a system clock of the data processing system based on the time data.

2. The system of claim 1, wherein the time data source is a global positioning system (GPS) compatible source that provides GPS time.

3. The system of claim 1, wherein the first signal comprises a pulse-per-second (PPS) signal, and wherein the message is a GPRMC compatible message.

4. A data processing system, comprising:

a processor;

a Peripheral Component Interface Express (PCIe) link; and

a time processing device coupled to the processor via the PCIe link, the time processing device including time processing logic and a time register, wherein the time processing logic is to

receive time data representing date and time from a time data source, and store the time data in the time register, wherein the time register comprises;

a first register to store date information,

a second register to store hour, minute, and second information, and

a third register to store millisecond, microsecond, and nanosecond information, and

wherein the processor retrieve e data from the time register via a single read instruction over the PCIe link and updates a system clock of the data processing system based on the time data.

5. The system of claim 4, wherein the time data source is a global positioning system (GPS) compatible source that provides GPS time.

6. The system of claim 5, wherein the time processing device further comprises a locking logic to lock at least one of the first register or the second register to prevent data stored the first register or the second register from changing, in response to a read request to read from the third register.

7. The system of claim 5, wherein in response to a read request for updating time, the time processing logic reads from the third register without reading from the first register and the second register, and wherein data stored in the first register and the second register is prefetched prior to receiving the read request before an OS scheduler is disabled.

8. The system of claim 7, wherein the second register is accessed on a boundary of a second and the first register is accessed on a boundary of a day.

9. A data processing system, comprising:

a processor;

a Peripheral Component Interface Express (PCIe) link;

a time processing device coupled to the processor via the PCIe link, the time processing device including time processing logic and a time register, wherein the time processing logic is to

receive time data representing date and time from a time data source, and

store the time data in the time register, wherein the processor retrieves the time data from the register via a single read instruction over the PCIe link and updates a system lock of the data processing system based on the time data, and

a memory hosting an operating system (OS) and a time processing driver executed within a kernel of the OS by the processor, wherein the time processing driver is to

suspend a scheduler of the OS,

read from the time register via a single instruction,

resume the scheduler of the OS, and

update the system clock.

10. The system of claim 9, wherein the time data source is a global positioning system (GPS) compatible source that provides GPS time.

11. A time processing device, comprising:

a Peripheral Component Interface Express (PCIe) link capable of coupling to a processor via a PCIe link;

a time register;

time processing logic coupled to the time register, wherein the time processing logic is to receive time data representing date and time from a time data source, and store the time data in the time register, wherein the processor retrieves the time data from the time register via a single read instruction over the PCIe link and updates a system clock associated with the processor based on the time data;

a first input to receive a first signal from the time data source, the first signal indicating that an update of the time data is available from the time data source;

a second input to receive a message having the updated time data from the time data source, wherein the time processing logic is to

detect the first signal received from the first input,

in response to the first signal, decode the time data received from the second input, and

store the decoded time data in the time register.

12. The device of claim 11, wherein the first signal comprises a pulse-per-second (PPS) signal, and wherein the message is a GPRMC compatible message.

13. The device of claim 11, wherein the time data source is a global positioning system (GPS) compatible source that provides GPS time.

14. A time processing device, comprising:

a Peripheral Component Interface Express (PCIe) link capable of coupling to a processor via a PCIe link;

a time register, wherein the time register comprises;

a first register to store date information,

a second register to store hour, minute, and second information, and

a third register to store millisecond, microsecond, and nanosecond information; and

time processing logic coupled to the time register, wherein the time processing logic is to

receive time data representing date and time from a time data source,

store the time data in the time register, wherein the processor retrieves the time data from the time register via a single read instruction over the PCIe link, and

update a system clock associated with the processor based on the time data.

15. The device of claim 14, further comprising a locking logic to lock at least one of the first register or the second register to prevent data stored the first register or the second register from changing, in response to a read request to read from the third register.

16. The device of claim 14, wherein in response to a read request for updating time, the time processing logic reads from the third register without reading from the first register and the second register, and wherein data stored in the first register and the second register is prefetched prior to receiving the read request.

17. The device of claim 16, wherein the second register is accessed on a boundary of a second and the first register is accessed on a boundary of a day.