Time tracking with trits

• US 10,163,471 B2
• Filed: 03/30/2017
• Issued: 12/25/2018
• Est. Priority Date: 03/30/2017
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kwok, Zion S.
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): Leboeuf, Jerome
• Application Number:
  US15/474,659
• Publication Number:
  US 20180286469A1
• Time in Patent Office: 635 Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global timer index from a global timer having a granularity, G. The timestamp circuitry is further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block. The demarcation voltage (VDM) selection circuitry is to fetch a combined count from a count store. The combined count represents a combined state. The combined state includes a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block.

Claims

1. A memory controller circuitry comprising:

a timestamp circuitry to capture a timer index from a timer having a granularity;

the timestamp circuitry further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block;

mode swap circuitry to identify a first composite count and a second compressed count;

a demarcation voltage (VDM) selection circuitry to fetch a combined count from a count store, the combined count representing a combined state, the combined state comprising a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block; and

reduction/expansion circuitry to expand the first composite count to a corresponding first composite state;

wherein;

the VDM selection circuitry is to fetch the first composite count and the second compressed count; and

the mode swap circuitry is to convert the second compressed count to a second composite state and to set the target individual state of the target sub-block to zero in response to a write request to the target sub-block, if the timestamp is not equal to the timer index.

2. The memory controller circuitry of claim 1, wherein the VDM selection circuitry is to determine an elapsed time based, at least in part, on the timer index, the timestamp and the target individual state.

3. The memory controller circuitry of claim 1, further comprising a reduction/expansion circuitry to expand a composite count into a composite state, the composite count comprising a number N2 bits, the composite state comprising a number N1 trits, the target individual state corresponding to one trit of the N1 trits, N2 less than 2*N1.

4. The memory controller circuitry of claim 2, wherein the VDM selection circuitry is to determine the elapsed time in response to a read request for the target sub-block and to select a first demarcation voltage (VDM1) if the elapsed time is less than the granularity or a second demarcation voltage (VDM2) if the elapsed time is greater than or equal to the granularity.

5. The memory controller circuitry of claim 1, wherein the VDM selection circuitry is to set the target individual state of the target sub-block to zero in response to a write to the target sub-block.

6. The memory controller circuitry of claim 5, wherein, if the timer index is not equal to the timestamp, the VDM selection circuitry is to increment an other trit in the composite state in response to the write to the target sub-block if the other trit is less than two and the timestamp circuitry is to associate the captured timer index with the memory block and store the captured timer index to a timestamp store.

7. The memory controller circuitry of claim 1, wherein the VDM selection circuitry is to update a trit if the trit is less than two, the reduction/expansion circuitry is to reduce the second composite state to a second composite count and the mode swap circuitry is to convert the first composite state to a first compressed count.

8. A method comprising:

capturing, by a timestamp circuitry, a timer index from a timer having a granularity;

fetching, by the timestamp circuitry, a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block;

fetching, by a demarcation voltage (VDM) selection circuitry, a combined count from a count store, the combined count representing a combined state, the combined state comprising a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block;

identifying, by mode swap circuitry, a first composite count and a second compressed count;

fetching, by the VDM selection circuitry, the first composite count and the second compressed count;

expanding, by reduction/expansion circuitry, the first composite count to a corresponding first composite state;

converting, by the mode swap circuitry, the second compressed count to a second composite state; and

setting, by the mode swap circuitry, the target individual state of the target sub-block to zero in response to a write request to the target sub-block, if the timestamp is not equal to the timer index.

9. The method of claim 8, further comprising determining, by the VDM selection circuitry, an elapsed time based, at least in part, on the timer index, the timestamp and the target individual state.

10. The method of claim 8, further comprising expanding, by a reduction/expansion circuitry, a composite count into a composite state, the composite count comprising a number N2 bits, the composite state comprising a number N1 trits, the target individual state corresponding to one trit of the N1 trits, N2 less than 2*N1.

11. The method of claim 9, further comprising determining, by the VDM selection circuitry, the elapsed time in response to a read request for the target sub-block and selecting, by the VDM selection circuitry, a first demarcation voltage (VDM1) if the elapsed time is less than the granularity or a second demarcation voltage (VDM2) if the elapsed time is greater than or equal to the granularity.

12. The method of claim 8, further comprising setting, by the VDM selection circuitry, the target individual state of the target sub-block to zero in response to a write to the target sub-block.

13. The method of claim 12, further comprising, if the timer index is not equal to the timestamp, incrementing, by the VDM selection circuitry, an other trit in the composite state in response to the write to the target sub-block if the other trit is less than two;

associating, by the timestamp circuitry, the captured timer index with the memory block; and

storing, by the timestamp circuitry, the captured timer index to a timestamp store.

14. The method of claim 8, further comprising updating, by the VDM selection circuitry, a trit if the trit is less than two;

reducing, by the reduction/expansion circuitry, the second composite state to a second composite count; and

converting, by the mode swap circuitry, the first composite state to a first compressed count.

15. A time tracking system comprising:

a processor circuitry;

a memory array comprising a plurality of memory blocks;

a memory circuitry comprising a count store and a timestamp store; and

a memory controller comprising;

a timestamp circuitry to capture a timer index from a timer having a granularity;

the timestamp circuitry further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block;

mode swap circuitry to identify a first composite count and a second compressed count;

a demarcation voltage (VDM) selection circuitry to fetch a combined count from the count store, the combined count representing a combined state, the combined state comprising a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block; and

reduction/expansion circuitry to expand the first composite count to a corresponding first composite state;

wherein;

the VDM selection circuitry is to fetch the first composite count and the second compressed count; and

the mode swap circuitry is to convert the second compressed count to a second composite state and to set the target individual state of the target sub-block to zero in response to a write request to the target sub-block, if the timestamp is not equal to the timer index.

16. The time tracking system of claim 15, wherein the VDM selection circuitry is to determine an elapsed time based, at least in part, on the timer index, the timestamp and the target individual state.

17. The time tracking system of claim 15, further comprising a reduction/expansion circuitry to expand a composite count into a composite state, the composite count comprising a number N2 bits, the composite state comprising a number N1 trits, the target individual state corresponding to one trit of the N1 trits, N2 less than 2*N1.

18. The time tracking system of claim 16, wherein the VDM selection circuitry is to determine the elapsed time in response to a read request for the target sub-block and to select a first demarcation voltage (VDM1) if the elapsed time is less than the granularity or a second demarcation voltage (VDM2) if the elapsed time is greater than or equal to the granularity.

19. The time tracking system of claim 15, wherein the VDM selection circuitry is to set the target individual state of the target sub-block to zero in response to a write to the target sub-block.

20. The time tracking system of claim 19, wherein, if the timer index is not equal to the timestamp, the VDM selection circuitry is to increment an other trit in the composite state in response to the write to the target sub-block if the other trit is less than two and the timestamp circuitry is to associate the captured timer index with the memory block and store the captured timer index to a timestamp store.

21. The time tracking system of claim 15, wherein the VDM selection circuitry is to update a trit if the trit is less than two, the reduction/expansion circuitry is to reduce the second composite state to a second composite count and the mode swap circuitry is to convert the first composite state to a first compressed count.