Method and apparatus for bipolar memory write-verify

• US 10,163,479 B2
• Filed: 06/06/2016
• Issued: 12/25/2018
• Est. Priority Date: 08/14/2015
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Transfer Technologies, Inc.
• Inventors: Berger, Neal, Louie, Ben, El-Baraji, Mourad
• Primary Examiner(s): Yoha, Connie
• Application Number:
  US15/174,482
• Publication Number:
  US 20170047107A1
• Time in Patent Office: 932 Days
• Field of Search: 365158, 365148, 36518522
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing

Abstract

An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Claims

1. A method for writing data to a memory device, said method comprising:

writing a bit of data into a memory cell, wherein said memory cell comprises a bit line and a source line, said writing comprising;

applying a first differential voltage bias across said bit and source lines provided said data bit is a first logic value; and

applying a second differential voltage bias across said bit and source lines provided said data bit is a second logic value, wherein said second differential voltage bias is opposite in polarity to said first differential voltage bias; and

verifying said bit of said memory cell by applying either said first or second differential voltage bias across said bit and source lines depending on the logic value of said bit.

2. The method of claim 1, wherein said memory cell comprises a bipolar memory element.

3. The method of claim 2 wherein said bipolar memory element comprises a magnetic tunnel junction.

4. The method of claim 2 wherein said bipolar memory element comprises a memristor.

5. The method of claim 2, the wherein the writing further comprises writing the bit into the bipolar memory element, wherein the bipolar memory element comprises chalcogenide glass.

6. The method of claim 2, wherein said memory cell further comprises a first bias circuit and wherein further the applying the first voltage differential bias further comprises applying the first voltage differential bias with a first bias circuit coupled to the source line and a second bias circuit coupled to the bit line.

7. The method of claim 2 further comprising detecting the logic value corresponding to the bit in the bipolar memory element, wherein the detecting is performed by a sense amplifier coupled to the source line.

8. The method of claim 2 further comprising detecting the logic value corresponding to the data bit in the bipolar memory element, wherein the detecting is performed by a sense amplifier coupled to the bit line.

9. The method as described in claim 1 wherein said verifying comprises:

applying said first differential voltage bias across said bit and sources lines provided said data bit is a first logic value; and

applying said second differential voltage bias across said bit and sources lines provided said data bit is a second logic value, wherein said second differential voltage bias is opposite in polarity compared to said first differential voltage value.

10. The method of claim 2, wherein said verifying further comprises reading said bit from a program latch.

11. The method of claim 10, wherein the applying the second voltage differential bias further comprises applying the second voltage differential bias using a bias circuit coupled to a mux, wherein the mux is coupled to the source line and the bit line and wherein further the mux selects whether to drive the voltage high on the source line or the bit line based on data in said program latch.

12. The method of claim 2 wherein said verifying further comprises detecting the logic value of said bit in the bipolar memory element using a sense amplifier coupled to the mux.

13. A method for writing data to a spin-transfer torque magnetic memory (STT-MRAM) device, said method comprising:

writing a bit of data into a memory cell, wherein said memory cell comprises a bit line and a source line and a magnetic tunnel junction (MTJ), said writing comprising;

applying a first differential voltage bias across said bit and source lines provided said data bit is a first logic value; and

applying a second differential voltage bias across said bit and source lines provided said data bit is a second logic value, wherein said second differential voltage bias is opposite in polarity to said first differential voltage bias; and

verifying said bit of said memory cell by applying either said first or second differential voltage bias across said bit and source lines depending on the logic value of said bit.

14. The method of claim 13, wherein the applying the first voltage differential bias further comprises applying the first voltage differential bias using a first bias circuit coupled to the source line and a second bias circuit coupled to the bit line.

15. The method of claim 13, wherein the applying the second voltage differential further comprises applying the second voltage differential with a first bias circuit coupled to the source line and a second bias circuit coupled to the bit line.

16. The method of claim 13 wherein said verifying further comprises detecting said logic value corresponding to the bit in the MTJ, wherein the detecting is performed using a sense amplifier coupled to the source line.

17. The method of claim 13 wherein said verifying further comprises detecting said logic value corresponding to the bit in the MTJ, wherein the detecting is performed using a sense amplifier coupled to the bit line.

18. The method of claim 13, wherein said verifying comprises reading said logic value from a program latch and wherein further the applying the first voltage differential bias or said second voltage differential bias of said verifying further comprises applying the first or second voltage differential bias using a mux, wherein the mux is coupled to the source line and the bit line, wherein the mux selects whether to drive the voltage high on the source line or the bit line based on said program latch.

19. The method of claim 18 further wherein said verifying comprises detecting the logic level corresponding to the bit in the MTJ using a sense amplifier coupled to the mux.

20. The method of claim 13 wherein said verifying comprises:

applying the first differential voltage bias across said bit and source lines provided said data bit is the first logic value; and

applying the second differential voltage bias across said bit and source lines provided said data bit is the second logic value.

21. A method for writing data to a spin-transfer torque magnetic memory (STT-MRAM) device, said method comprising:

writing a bit of data into a memory cell, wherein said memory cell comprises a bit line and a source line and a magnetic tunnel junction (MTJ), said writing comprising;

applying a first differential voltage bias across said bit and source lines provided said data bit is a first logic value; and

applying a second differential voltage bias across said bit and source lines provided said data bit is a second logic value, wherein said second differential voltage bias is opposite in polarity to said first differential voltage bias; and

verifying said bit of said memory cell, said verifying comprising;

reading said bit of data from a latch; and

applying either said first or second differential voltage bias across said bit and source lines depending on the logic value of said bit.

22. The method of claim 21, wherein said applying of said verifying further comprises:

applying the first differential voltage bias across said bit and source lines provided said data bit is the first logic value; and

applying the second differential voltage bias across said bit and source lines provided said data bit is the second logic value.

23. The method of claim 22, further comprising reading said bit from said memory cell, wherein said reading comprises applying either first differential voltage bias or second differential voltage bias across said bit and source lines.